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FDC6301 PDF预览

FDC6301

更新时间: 2024-09-13 22:49:03
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD /
页数 文件大小 规格书
4页 77K
描述
Dual N-Channel , Digital FET

FDC6301 数据手册

 浏览型号FDC6301的Datasheet PDF文件第2页浏览型号FDC6301的Datasheet PDF文件第3页浏览型号FDC6301的Datasheet PDF文件第4页 
July 1997  
FDC6301N  
Dual N-Channel , Digital FET  
General Description  
Features  
25 V, 0.22 A continuous, 0.5 A Peak.  
These dual N-Channel logic level enhancement mode field  
effect transistors are produced using Fairchild 's proprietary,  
high cell density, DMOS technology. This very high density  
process is especially tailored to minimize on-state resistance.  
This device has been designed especially for low voltage  
applications as a replacement for digital transistors. Since bias  
resistors are not required, these N-Channel FET's can replace  
several digital transistors, with a variety of bias resistors.  
RDS(ON) = 5 W @ VGS= 2.7 V  
RDS(ON) = 4 W @ VGS= 4.5 V.  
Very low level gate drive requirements allowing direct  
operation in 3V circuits. VGS(th) < 1.5V.  
Gate-Source Zener for ESD ruggedness.  
>6kV Human Body Model.  
SuperSOTTM-8  
SuperSOTTM-6  
SOT-23  
SO-8  
SOIC-16  
SOT-223  
Mark: .301  
Vcc  
INVERTER APPLICATION  
4
3
D
OUT  
2
5
6
IN  
G
S
1
GND  
Absolute Maximum Ratings TA = 25oC unless other wise noted  
Symbol Parameter  
FDC6301N  
Units  
VDSS, VCC Drain-Source Voltage, Power Supply Voltage  
25  
8
V
V
A
VGSS, VIN Gate-Source Voltage, VIN  
Drain/Output Current  
- Continuous  
- Pulsed  
0.22  
0.5  
ID, IOUT  
PD  
Maximum Power Dissipation  
(Note 1a)  
(Note 1b)  
0.9  
W
0.7  
TJ,TSTG  
ESD  
Operating and Storage Temperature Range  
-55 to 150  
6.0  
°C  
kV  
Electrostatic Discharge Rating MIL-STD-883D  
Human Body Model (100pf / 1500 Ohm)  
THERMAL CHARACTERISTICS  
RqJA  
RqJC  
Thermal Resistance, Junction-to-Ambient  
Thermal Resistance, Junction-to-Case  
(Note 1a)  
(Note 1)  
140  
60  
°C/W  
°C/W  
© 1997 Fairchild Semiconductor Corporation  
FDC6301N Rev.C  

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