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FDC6303 PDF预览

FDC6303

更新时间: 2024-11-04 22:49:03
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD /
页数 文件大小 规格书
4页 75K
描述
Digital FET, Dual N-Channel

FDC6303 数据手册

 浏览型号FDC6303的Datasheet PDF文件第2页浏览型号FDC6303的Datasheet PDF文件第3页浏览型号FDC6303的Datasheet PDF文件第4页 
August 1997  
FDC6303N  
Digital FET, Dual N-Channel  
General Description  
Features  
25 V, 0.68 A continuous, 2 A Peak.  
These dual N-Channel logic level enhancement mode field  
effect transistors are produced using Fairchild's proprietary,  
high cell density, DMOS technology. This very high density  
process is especially tailored to minimize on-state  
resistance. This device has been designed especially for  
RDS(ON) = 0.6 W @ VGS = 2.7 V  
RDS(ON) = 0.45 W @ VGS= 4.5 V.  
Very low level gate drive requirements allowing direct  
operation in 3V circuits. VGS(th) < 1.5 V.  
low voltage applications as  
a replacement for digital  
transistors in load switching applications. Since bias  
resistors are not required this one N-Channel FET can  
replace several digital transistors with different bias  
resistors like the IMHxA series.  
Gate-Source Zener for ESD ruggedness.  
>6kV Human Body Model  
Replace multiple NPN digital transistors (IMHxA series)  
with one DMOS FET.  
SuperSOTTM-8  
SuperSOTTM-6  
SOT-23  
SO-8  
SOIC-16  
SOT-223  
Mark: .303  
4
3
2
1
5
6
Absolute Maximum Ratings  
TA = 25°C unless otherwise noted  
Symbol Parameter  
FDC6303N  
Units  
VDSS  
VGSS  
ID  
Drain-Source Voltage  
Gate-Source Voltage  
Drain Current  
25  
8
V
V
A
- Continuous  
- Pulsed  
0.68  
2
PD  
Maximum Power Dissipation  
(Note 1a)  
(Note 1b)  
0.9  
W
0.7  
TJ,TSTG  
ESD  
Operating and Storage Temperature Range  
-55 to 150  
6.0  
°C  
kV  
Electrostatic Discharge Rating MIL-STD-883D  
Human Body Model (100pf / 1500 Ohm)  
THERMAL CHARACTERISTICS  
Thermal Resistance, Junction-to-Ambient  
Thermal Resistance, Junction-to-Case  
(Note 1a)  
(Note 1)  
140  
60  
°C/W  
°C/W  
RqJA  
RqJC  
© 1997 Fairchild Semiconductor Corporation  
FDC6303N Rev.C  

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