PSMN6R0-30YL

更新时间： 2024-09-14 06:05:35

品牌	Logo	应用领域
恩智浦 - NXP		晶体晶体管开关脉冲
页数	文件大小	规格书
14页	219K
描述
N-channel TrenchMOS logic level FET

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PSMN6R0-30YL 数据手册

PSMN6R0-30YL

N-channel TrenchMOS logic level FET

Rev. 03 — 4 Januari 2010

Product data sheet

1. Product profile

1.1 General description

Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic

package using TrenchMOS technology. This product is designed and qualified for use in

industrial and communications applications.

1.2 Features and benefits

High efficiency due to low switching

Suitable for logic level gate drive

and conduction losses

sources

1.3 Applications

Class-D amplifiers

Motor control

DC-to-DC converters

Server power supplies

1.4 Quick reference data

Table 1.

Quick reference

Symbol Parameter

Conditions

drain-source voltage T_j≥ 25 °C; T_j≤ 175 °C

Min

Typ

Max Unit

V_DS

I_D

drain current

T_mb= 25 °C; V_GS= 10 V;

see Figure 1

P_tot

total power

dissipation

T_mb= 25 °C; see Figure 2

Dynamic characteristics

Q_GD

gate-drain charge

total gate charge

V_GS= 4.5 V; I_D= 10 A;

V_DS= 12 V; see Figure 14 and 15

3.08

Q_G(tot)

Static characteristics

R_DSon

drain-source

V_GS= 10 V; I_D= 15 A; T_j= 25 °C

4.26

mΩ

on-state resistance

12 3 4 5 6 7...14

中文翻译

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