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NSVMMUN2230LT1G PDF预览

NSVMMUN2230LT1G

更新时间： 2024-12-01 11:01:35
品牌 Logo 应用领域
安森美 - ONSEMI 小信号双极晶体管数字晶体管
页数 文件大小 规格书
12页 144K
描述
NPN 双极数字晶体管 (BRT)

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中文翻译

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NSVMMUN2230LT1G 技术参数

是否无铅： 不含铅生命周期：Active
Reach Compliance Code：compliantECCN代码：EAR99
Factory Lead Time：4 weeks风险等级：5.71
JESD-609代码：e3湿度敏感等级：1
峰值回流温度（摄氏度）：NOT SPECIFIED端子面层：Tin (Sn)
处于峰值回流温度下的最长时间：NOT SPECIFIEDBase Number Matches：1

NSVMMUN2230LT1G 数据手册

 浏览型号NSVMMUN2230LT1G的Datasheet PDF文件第2页浏览型号NSVMMUN2230LT1G的Datasheet PDF文件第3页浏览型号NSVMMUN2230LT1G的Datasheet PDF文件第4页浏览型号NSVMMUN2230LT1G的Datasheet PDF文件第5页浏览型号NSVMMUN2230LT1G的Datasheet PDF文件第6页浏览型号NSVMMUN2230LT1G的Datasheet PDF文件第7页 
MUN2230, MMUN2230L,  
MUN5230, DTC113EE,  
DTC113EM3, NSBC113EF3  
Digital Transistors (BRT)  
R1 = 1 kW, R2 = 1 kW  
http://onsemi.com  
PIN CONNECTIONS  
NPN Transistors with Monolithic Bias  
Resistor Network  
PIN 3  
COLLECTOR  
(OUTPUT)  
This series of digital transistors is designed to replace a single  
device and its external resistor bias network. The Bias Resistor  
Transistor (BRT) contains a single transistor with a monolithic bias  
network consisting of two resistors; a series base resistor and a base−  
emitter resistor. The BRT eliminates these individual components by  
integrating them into a single device. The use of a BRT can reduce  
both system cost and board space.  
PIN 1  
BASE  
(INPUT)  
R1  
R2  
PIN 2  
EMITTER  
(GROUND)  
Features  
MARKING DIAGRAMS  
• Simplifies Circuit Design  
• Reduces Board Space  
• Reduces Component Count  
• S and NSV Prefix for Automotive and Other Applications Requiring  
Unique Site and Control Change Requirements; AEC-Q101 Qualified  
and PPAP Capable  
SC−59  
CASE 318D  
STYLE 1  
XX MG  
G
1
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS  
Compliant  
SOT−23  
CASE 318  
STYLE 6  
XXX MG  
G
1
MAXIMUM RATINGS (T = 25°C)  
A
Rating  
Collector−Base Voltage  
Collector−Emitter Voltage  
Collector Current − Continuous  
Input Forward Voltage  
Symbol  
Max  
50  
Unit  
Vdc  
SC−70/SOT−323  
CASE 419  
XX MG  
V
CBO  
CEO  
G
STYLE 3  
V
50  
Vdc  
1
I
C
100  
10  
mAdc  
Vdc  
SC−75  
CASE 463  
STYLE 1  
V
IN(fwd)  
XX M  
XX M  
Input Reverse Voltage  
V
IN(rev)  
10  
Vdc  
1
Stresses exceeding Maximum Ratings may damage the device. Maximum  
Ratings are stress ratings only. Functional operation above the Recommended  
Operating Conditions is not implied. Extended exposure to stresses above the  
Recommended Operating Conditions may affect device reliability.  
SOT−723  
CASE 631AA  
STYLE 1  
1
SOT−1123  
CASE 524AA  
STYLE 1  
X M  
1
XXX  
M
G
=
=
=
Specific Device Code  
Date Code*  
Pb−Free Package  
(Note: Microdot may be in either location)  
*Date Code orientation may vary depending  
upon manufacturing location.  
ORDERING INFORMATION  
See detailed ordering, marking, and shipping information in  
the package dimensions section on page 2 of this data sheet.  
© Semiconductor Components Industries, LLC, 2013  
1
Publication Order Number:  
February, 2013 − Rev. 1  
DTC113E/D  
1234567...12

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