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NSVMMUN2237LT1G PDF预览

NSVMMUN2237LT1G

更新时间： 2023-06-19 14:32:11
品牌 Logo 应用领域
安森美 - ONSEMI 小信号双极晶体管数字晶体管
页数 文件大小 规格书
11页 92K
描述
NPN 双极数字晶体管 (BRT)

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中文翻译

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NSVMMUN2237LT1G 技术参数

是否无铅：不含铅生命周期：Active
Reach Compliance Code：compliantFactory Lead Time：4 weeks
风险等级：5.75Is Samacsys：N
JESD-609代码：e3湿度敏感等级：1
端子面层：Tin (Sn)Base Number Matches：1

NSVMMUN2237LT1G 数据手册

 浏览型号NSVMMUN2237LT1G的Datasheet PDF文件第2页浏览型号NSVMMUN2237LT1G的Datasheet PDF文件第3页浏览型号NSVMMUN2237LT1G的Datasheet PDF文件第4页浏览型号NSVMMUN2237LT1G的Datasheet PDF文件第5页浏览型号NSVMMUN2237LT1G的Datasheet PDF文件第6页浏览型号NSVMMUN2237LT1G的Datasheet PDF文件第7页 
DTC114EET1 Series  
Bias Resistor Transistor  
NPN Silicon Surface Mount Transistor  
with Monolithic Bias Resistor Network  
This new series of digital transistors is designed to replace a single  
device and its external resistor bias network. The BRT (Bias Resistor  
Transistor) contains a single transistor with a monolithic bias network  
consisting of two resistors; a series base resistor and a base−emitter  
resistor. The BRT eliminates these individual components by  
integrating them into a single device. The use of a BRT can reduce  
both system cost and board space. The device is housed in the  
SC−75/SOT−416 package which is designed for low power surface  
mount applications.  
http://onsemi.com  
NPN SILICON  
BIAS RESISTOR TRANSISTORS  
PIN 3  
COLLECTOR  
(OUTPUT)  
Features  
PIN 1  
R1  
• Simplifies Circuit Design  
BASE  
(INPUT)  
• Reduces Board Space  
R2  
• Reduces Component Count  
PIN 2  
EMITTER  
(GROUND)  
• The SC−75/SOT−416 Package Can be Soldered Using Wave or  
Reflow  
• The Modified Gull−Winged Leads Absorb Thermal Stress During  
Soldering Eliminating the Possibility of Damage to the Die  
• Pb−Free Packages are Available  
3
2
1
MAXIMUM RATINGS (T = 25°C unless otherwise noted)  
A
Rating  
Collector-Base Voltage  
Collector-Emitter Voltage  
Collector Current  
Symbol  
Value  
50  
Unit  
Vdc  
V
V
CBO  
CEO  
SC−75 (SOT−416)  
CASE 463  
50  
Vdc  
STYLE 1  
I
100  
mAdc  
C
THERMAL CHARACTERISTICS  
MARKING DIAGRAM  
Rating  
Symbol  
Value  
Unit  
Total Device Dissipation,  
P
D
FR−4 Board (Note 1) @ T = 25°C  
Derate above 25°C  
200  
1.6  
mW  
mW/°C  
A
xx M G  
Thermal Resistance,  
Junction−to−Ambient (Note 1)  
R
600  
°C/W  
q
JA  
G
Total Device Dissipation,  
P
D
FR−4 Board (Note 2) @ T = 25°C  
Derate above 25°C  
300  
2.4  
mW  
mW/°C  
A
xx  
=
Specific Device Code  
xx = (Refer to page 2)  
Date Code*  
Thermal Resistance,  
Junction−to−Ambient (Note 2)  
R
400  
°C/W  
q
JA  
M
G
=
=
Pb−Free Package  
Junction and Storage Temperature  
Range  
T , T  
J
−55 to +150  
°C  
stg  
(Note: Microdot may be in either location)  
*Date Code orientation may vary depending  
upon manufacturing location.  
Stresses exceeding Maximum Ratings may damage the device. Maximum  
Ratings are stress ratings only. Functional operation above the Recommended  
Operating Conditions is not implied. Extended exposure to stresses above the  
Recommended Operating Conditions may affect device reliability.  
1. FR−4 @ Minimum Pad  
ORDERING INFORMATION  
See detailed ordering, marking, and shipping information in  
the package dimensions section on page 2 of this data sheet.  
2. FR−4 @ 1.0 × 1.0 Inch Pad  
©
Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
March, 2006 − Rev. 8  
DTC114EET1/D  
1234567...11

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