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NSVMMUN2232LT3G PDF预览

NSVMMUN2232LT3G

更新时间: 2023-06-19 14:32:11
品牌 Logo 应用领域
安森美 - ONSEMI 小信号双极晶体管数字晶体管
页数 文件大小 规格书
10页 82K
描述
NPN 双极数字晶体管 (BRT)

NSVMMUN2232LT3G 技术参数

是否无铅: 不含铅生命周期:Active
针数:3Reach Compliance Code:compliant
ECCN代码:EAR99Factory Lead Time:4 weeks
风险等级:5.8最大集电极电流 (IC):0.1 A
最小直流电流增益 (hFE):15JESD-609代码:e3
湿度敏感等级:1元件数量:1
极性/信道类型:NPN最大功率耗散 (Abs):0.4 W
子类别:BIP General Purpose Small Signal表面贴装:YES
端子面层:Tin (Sn)晶体管元件材料:SILICON

NSVMMUN2232LT3G 数据手册

 浏览型号NSVMMUN2232LT3G的Datasheet PDF文件第2页浏览型号NSVMMUN2232LT3G的Datasheet PDF文件第3页浏览型号NSVMMUN2232LT3G的Datasheet PDF文件第4页浏览型号NSVMMUN2232LT3G的Datasheet PDF文件第5页浏览型号NSVMMUN2232LT3G的Datasheet PDF文件第6页浏览型号NSVMMUN2232LT3G的Datasheet PDF文件第7页 
DTC114EM3T5G Series  
Digital Transistors (BRT)  
NPN Silicon Surface Mount Transistors  
with Monolithic Bias Resistor Network  
This new series of digital transistors is designed to replace a single  
device and its external resistor bias network. The digital transistor  
contains a single transistor with a monolithic bias network consisting  
of two resistors; a series base resistor and a base−emitter resistor. The  
digital transistor eliminates these individual components by  
integrating them into a single device. The use of a digital transistor can  
reduce both system cost and board space. The device is housed in the  
SOT−723 package which is designed for low power surface mount  
applications.  
http://onsemi.com  
NPN SILICON DIGITAL  
TRANSISTORS  
PIN 3  
COLLECTOR  
(OUTPUT)  
Features  
PIN 1  
BASE  
(INPUT)  
R1  
R2  
Simplifies Circuit Design  
Reduces Board Space  
Reduces Component Count  
PIN 2  
EMITTER  
(GROUND)  
The SOT−723 Package can be Soldered using Wave or Reflow.  
Available in 4 mm, 8000 Unit Tape & Reel  
These are Pb−Free Devices  
MAXIMUM RATINGS (T = 25°C unless otherwise noted)  
A
3
SOT−723  
CASE 631AA  
STYLE 1  
Rating  
Collector-Base Voltage  
Collector-Emitter Voltage  
Collector Current  
Symbol  
Value  
50  
Unit  
Vdc  
V
V
CBO  
CEO  
2
1
50  
Vdc  
I
100  
mAdc  
C
Maximum ratings are those values beyond which device damage can occur.  
Maximum ratings applied to the device are individual stress limit values (not  
normal operating conditions) and are not valid simultaneously. If these limits are  
exceeded, device functional operation is not implied, damage may occur and  
reliability may be affected.  
MARKING DIAGRAM  
xx  
xx = Specific Device Code  
(See Marking Table on page 2)  
M = Date Code  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 2 of this data sheet.  
©
Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
March, 2006 − Rev. 3  
DTC114EM3/D  

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