Datasheet > 74V2G00_03

74V2G00_03

更新时间： 2024-11-04 03:21:59

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		输入元件
页数	文件大小	规格书
7页	133K
描述
DUAL 2-INPUT NAND GATE

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中文翻译

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数据手册

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74V2G00_03 数据手册

74V2G00

DUAL 2-INPUT NAND GATE

■

HIGH SPEED: t = 3.7ns (TYP.) at V = 5V

PD CC

LOW POWER DISSIPATION:

= 1µA(MAX.) at T = 25°C

■

HIGH NOISE IMMUNITY:

= V = 28% V (MIN.)

NIH

NIL

■

POWER DOWN PROTECTION ON INPUTS

SOT23-8L

SYMMETRICAL OUTPUT IMPEDANCE:

|I | = I = 8mA (MIN)

■

BALANCED PROPAGATION DELAYS:

ORDER CODES

PLH

PHL

PACKAGE

T & R

OPERATING VOLTAGE RANGE:

(OPR) = 2V to 5.5V

SOT23-8L

74V2G00STR

IMPROVED LATCH-UP IMMUNITY

The internal circuit is composed of 3 stages

including buffer output, which provide high noise

immunity and stable output.

DESCRIPTION

The V2G00 is an advanced high-speed CMOS

SINGLE 2-INPUT NAND GATE fabricated with

sub-micron silicon gate and double-layer metal

Power down protection is provided on all inputs

and 0 to 7V can be accepted on inputs with no

regard to the supply voltage. This device can be

used to interface 5V to 3V.

wiring C MOS technology.

PIN CONNECTION AND IEC LOGIC SYMBOLS

October 2003

1/7

12 3 4 5 6 7

中文翻译

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