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74V2G00STR PDF预览

74V2G00STR

更新时间: 2024-01-23 03:31:59
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 栅极触发器逻辑集成电路光电二极管输入元件
页数 文件大小 规格书
6页 46K
描述
DUAL 2-INPUT NAND GATE

74V2G00STR 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Obsolete零件包装代码:SOT-23
包装说明:SOT-23, 8 PIN针数:8
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.81Is Samacsys:N
系列:74VJESD-30 代码:R-PDSO-G8
长度:2.9 mm逻辑集成电路类型:NAND GATE
最大I(ol):0.004 A湿度敏感等级:1
功能数量:2输入次数:2
端子数量:8最高工作温度:85 °C
最低工作温度:-55 °C封装主体材料:PLASTIC/EPOXY
封装代码:LSSOP封装等效代码:TSSOP8,.1
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, LOW PROFILE, SHRINK PITCH
包装方法:TAPE AND REEL峰值回流温度(摄氏度):260
电源:2/6 VProp。Delay @ Nom-Sup:13 ns
传播延迟(tpd):13 ns认证状态:Not Qualified
施密特触发器:NO座面最大高度:1.45 mm
子类别:Gates最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:OTHER端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:1.625 mm
Base Number Matches:1

74V2G00STR 数据手册

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74V2G00  
DUAL 2-INPUT NAND GATE  
HIGH SPEED:tPD =3.7ns (TYP.) atVCC = 5V  
LOW POWER DISSIPATION:  
I
CC =1 µA (MAX.) at TA =25 oC  
HIGH NOISEIMMUNITY:  
NIH = VNIL =28% VCC (MIN.)  
POWERDOWN PROTECTIONON INPUTS  
AND OUTPUTS  
SYMMETRICAL OUTPUT IMPEDANCE:  
|IOH| = IOL = 8 mA (MIN)  
BALANCEDPROPAGATIONDELAYS:  
tPLH tPHL  
V
SOT23-8L  
ORDER CODES  
PACKAGE  
TUBE  
T & R  
SOT23-8L  
74V2G00STR  
wiring C2MOS technology.  
The internal circuit is composed of 3 stages  
including buffer output, which provide high noise  
immunity and stable output.  
OPERATING VOLTAGERANGE:  
VCC (OPR)= 2V to 5.5V  
IMPROVED LATCH-UP IMMUNITY  
DESCRIPTION  
Power down protection is provided on all inputs  
and outputs and 0 to 7V can be accepted on  
inputs with no regard to the supply voltage. This  
device can be used to interface 5V to 3V.  
The 74V2G00 is an advanced high-speed CMOS  
DUAL 2-INPUT NAND GATE fabricated with  
sub-micron silicon gate and double-layer metal  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
1/6  
June 2000  

74V2G00STR 替代型号

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