Datasheet > 74V2G08CTR

74V2G08CTR

更新时间： 2024-11-03 23:24:35

品牌	Logo	应用领域
其他 - ETC		触发器逻辑集成电路光电二极管输入元件栅
页数	文件大小	规格书
9页	68K
描述
LOGIC GATE\|DUAL 2-INPUT OR\|CMOS\|TSSOP\|8PIN\|PLASTIC

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中文翻译

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数据手册

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74V2G08CTR 数据手册

74V2G08

DUAL 2-INPUT AND GATE

■

HIGH SPEED: t = 3.8ns (TYP.) at V = 5V

PD CC

LOW POWER DISSIPATION:

= 1µA(MAX.) at T =25°C

■

HIGH NOISE IMMUNITY:

= V = 28% V (MIN.)

NIH

NIL

■

POWER DOWN PROTECTION ON INPUTS

SYMMETRICAL OUTPUT IMPEDANCE:

SOT23-8L

SOT323-8L

T & R

|I | = I = 8mA (MIN) at V = 4.5V

■

BALANCED PROPAGATION DELAYS:

ORDER CODES

PLH

PHL

OPERATING VOLTAGE RANGE:

(OPR) = 2V to 5.5V

PACKAGE

SOT23-8L

74V2G08STR

74V2G08CTR

IMPROVED LATCH-UP IMMUNITY

SOT323-8L

DESCRIPTION

Power down protection is provided on all inputs

and 0 to 7V can be accepted on inputs with no

regard to the supply voltage. This device can be

used to interface 5V to 3V.

The 74V2G08 is an advanced high-speed CMOS

DUAL 2-INPUT AND GATE fabricated with

sub-micron silicon gate and double-layer metal

wiring C MOS technology.

The internal circuit is composed of 2 stages

including buffer output, which provide high noise

immunity and stable output.

PIN CONNECTION AND IEC LOGIC SYMBOLS

May 2002

1/9

12 3 4 5 6 7...9

中文翻译

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