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74V2G132STR PDF预览

74V2G132STR

更新时间: 2024-11-04 04:01:11
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 输入元件
页数 文件大小 规格书
9页 193K
描述
DUAL 2-INPUT SHMITT TRIGGER NAND GATE

74V2G132STR 数据手册

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74V2G132  
DUAL 2-INPUT SHMITT TRIGGER NAND GATE  
PRELIMINARY DATA  
HIGH SPEED: t = 3.0ns (TYP.) at V = 5V  
PD CC  
LOW POWER DISSIPATION:  
I
= 1µA(MAX.) at T =25°C  
CC  
A
TYPICAL HYSTERESIS:  
V = 800mV at V = 4.5V  
H
CC  
V = 500mV at V = 3.0V  
H
CC  
SOT23-8L  
SOT323-8L  
T & R  
POWER DOWN PROTECTION ON INPUTS  
AND OUTPUTS  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 8mA (MIN) at V = 4.5V  
ORDER CODES  
OH  
OL  
CC  
II | = I = 4mA (MIN) at V = 3.0V  
OH  
OL  
CC  
PACKAGE  
BALANCED PROPAGATION DELAYS:  
SOT23-8L  
74V2G132STR  
74V2G132CTR  
t
t
PLH  
PHL  
SOT323-8L  
OPERATING VOLTAGE RANGE:  
(OPR) = 2V to 5.5V  
V
CC  
IMPROVED LATCH-UP IMMUNITY  
The internal circuit is composed of 3 stages  
including buffer output, which provide high noise  
immunity and stable output.  
DESCRIPTION  
The 74V2G132 is an advanced high-speed CMOS  
SINGLE 2-INPUT NAND GATE fabricated with  
sub-micron silicon gate and double-layer metal  
Power down protection is provided on all inputs  
and 0 to 7V can be accepted on inputs with no  
regard to the supply voltage. This device can be  
used to interface 5V to 3V.  
2
wiring C MOS tecnology.  
Pin configuration and function are the same as  
those of the 74V2G00 but the 74V2G132 has  
hysteresis.  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
November 2001  
1/9  
This is preliminary information on a new product now in development are or undergoing evaluation. Details subject to change without notice.  

74V2G132STR 替代型号

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