Datasheet > 74V2G14CTR

74V2G14CTR

更新时间： 2024-11-03 23:24:35

品牌	Logo	应用领域
其他 - ETC		/
页数	文件大小	规格书
10页	72K
描述
LOGIC GATE\|TRIPLE INVERTER\|CMOS\|TSSOP\|8PIN\|PLASTIC

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数据手册

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74V2G14CTR 数据手册

74V2G14

TRIPLE SCHMITT INVERTER

■

HIGH SPEED: t = 3.0ns (TYP.) at V = 5V

PD CC

LOW POWER DISSIPATION:

= 1µA(MAX.) at T =25°C

■

TYPICAL HYSTERESIS:

= 800mV at V = 4.5V

= 500mV at V = 3.0V

SOT23-8L

SOT323-8L

T & R

■

POWER DOWN PROTECTION ON INPUTS

AND OUTPUTS

SYMMETRICAL OUTPUT IMPEDANCE:

|I | = I = 8mA (MIN) at V = 4.5V

ORDER CODES

II | = I = 4mA (MIN) at V = 3.0V

PACKAGE

■

BALANCED PROPAGATION DELAYS:

SOT23-8L

74V2G14STR

74V2G14CTR

PLH

PHL

SOT323-8L

OPERATING VOLTAGE RANGE:

(OPR) = 2V to 5.5V

IMPROVED LATCH-UP IMMUNITY

Pin configuration and function are the same as

those of the 74V2G04, but 74V2G14 has

hysteresis on inputs.

DESCRIPTION

The 74V2G14 is an advanced high-speed CMOS

TRIPLE SCHMITT TRIGGER INVERTER

fabricated with sub-micron silicon gate and

This device can be used to interface 5V to 3V

systems and it is ideal for portable applications

like personal digital assistant, camcorder and all

battery-powered equipment.

double-layer metal wiring C MOS tecnology.

The internal circuit is composed of 3 stages

including buffer output, which provide high noise

immunity and stable output.

All inputs and outputs are equipped with

protection circuits against static discharge, giving

them ESD immunity and transient excess voltage.

Power down protection is provided on all inputs

and outputs and 0 to 7V can be accepted on

inputs with no regard to the supply voltage.

PIN CONNECTION AND IEC LOGIC SYMBOLS

May 2002

1/10

12 3 4 5 6 7...10

中文翻译

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