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74V2T02CTR PDF预览

74V2T02CTR

更新时间: 2024-02-12 03:09:37
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 输入元件
页数 文件大小 规格书
7页 128K
描述
74V SERIES, DUAL 2-INPUT NOR GATE, PDSO8, SOT-323, 8 PIN

74V2T02CTR 技术参数

生命周期:Obsolete零件包装代码:SC-70
包装说明:SOT-323, 8 PIN针数:8
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.84系列:74V
JESD-30 代码:R-PDSO-G8长度:2 mm
逻辑集成电路类型:NOR GATE最大I(ol):0.008 A
功能数量:2输入次数:2
端子数量:8最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP8,.09,20
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法:TAPE AND REEL电源:5 V
Prop。Delay @ Nom-Sup:9.5 ns传播延迟(tpd):9.5 ns
认证状态:Not Qualified施密特触发器:NO
座面最大高度:1.1 mm子类别:Gates
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子形式:GULL WING端子节距:0.5 mm
端子位置:DUAL宽度:1.25 mm
Base Number Matches:1

74V2T02CTR 数据手册

 浏览型号74V2T02CTR的Datasheet PDF文件第2页浏览型号74V2T02CTR的Datasheet PDF文件第3页浏览型号74V2T02CTR的Datasheet PDF文件第4页浏览型号74V2T02CTR的Datasheet PDF文件第5页浏览型号74V2T02CTR的Datasheet PDF文件第6页浏览型号74V2T02CTR的Datasheet PDF文件第7页 
74V2T02  
DUAL 2-INPUT NOR GATE  
HIGH SPEED: t = 5.1ns (TYP.) at V = 5V  
PD CC  
LOW POWER DISSIPATION:  
I
= 1µA(MAX.) at T = 25°C  
CC  
A
COMPATIBLE WITH TTL OUTPUTS:  
= 2V (MIN), V = 0.8V (MAX)  
V
IH  
IL  
POWER DOWN PROTECTION ON INPUTS  
SOT23-8L  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 8mA (MIN) at V = 4.5V  
OH  
OL  
CC  
BALANCED PROPAGATION DELAYS:  
ORDER CODES  
t
t
PLH  
PHL  
PACKAGE  
SOT23-8L  
T & R  
OPERATING VOLTAGE RANGE:  
(OPR) = 4.5V to 5.5V  
74V2T02STR  
V
CC  
IMPROVED LATCH-UP IMMUNITY  
The internal circuit is composed of 3 stages  
including buffer output, which provide high noise  
immunity and stable output.  
DESCRIPTION  
The 74V2T02 is an advanced high-speed CMOS  
DUAL 2-INPUT NOR GATE fabricated with  
sub-micron silicon gate and double-layer metal  
Power down protection is provided on all inputs  
and 0 to 7V can be accepted on inputs with no  
regard to the supply voltage. This device can be  
used to interface 5V to 3V.  
2
wiring C MOS technology.  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
June 2003  
1/7  

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