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74V2G70

更新时间： 2024-01-16 11:44:13

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		/
页数	文件大小	规格书
8页	132K
描述
TRIPLE BUFFER

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中文翻译

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数据手册

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74V2G70 数据手册

74V2G70

TRIPLE BUFFER

■

HIGH SPEED: t = 3.0ns (TYP.) at V = 5V

PD CC

LOW POWER DISSIPATION:

= 1µA(MAX.) at T = 25°C

■

HIGH NOISE IMMUNITY:

= V = 28% V (MIN.)

POWER DOWN PROTECTION ON INPUTS

AND OUTPUTS

NIH

NIL

SOT23-8L

SYMMETRICAL OUTPUT IMPEDANCE:

|I | = I = 8mA (MIN) at V = 4.5V

II | = I = 4mA (MIN) at V = 3.0V

BALANCED PROPAGATION DELAYS:

ORDER CODES

PACKAGE

■

T & R

PLH

PHL

SOT23-8L

74V2G70STR

OPERATING VOLTAGE RANGE:

(OPR) = 2V to 5.5V

Power down protection is provided on all inputs

and outputs and 0 to 7V can be accepted on

inputs with no regard to the supply voltage.

This device can be used to interface 5V to 3V

systems and it is ideal for portable applications

like personal digital assistant, camcorder and all

battery-powered equipment.

All inputs and outputs are equipped with

protection circuits against static discharge, giving

them ESD immunity and transient excess voltage.

IMPROVED LATCH-UP IMMUNITY

DESCRIPTION

The 74V2G70 is an advanced high-speed CMOS

TRIPLE NOT INVERTED BUFFER fabricated with

sub-micron silicon gate and double-layer metal

wiring C MOS technology.

The internal circuit is composed of 3 stages

including buffer output, which provide high noise

immunity and stable output.

PIN CONNECTION AND IEC LOGIC SYMBOLS

June 2003

1/8

12 3 4 5 6 7 8

中文翻译

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