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74V2G241STR PDF预览

74V2G241STR

更新时间: 2024-10-01 08:04:43
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 总线驱动器总线收发器逻辑集成电路光电二极管
页数 文件大小 规格书
9页 102K
描述
DUAL BUS BUFFER NON INVERTED (3-STATE)

74V2G241STR 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOT-23包装说明:SOT-23, 8 PIN
针数:8Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.84
控制类型:ENABLE LOW/HIGH系列:74V
JESD-30 代码:R-PDSO-G8JESD-609代码:e0
长度:2.9 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER最大I(ol):0.00005 A
湿度敏感等级:1位数:1
功能数量:2端口数量:2
端子数量:8最高工作温度:125 °C
最低工作温度:-55 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:LSSOP封装等效代码:TSSOP8,.1
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, LOW PROFILE, SHRINK PITCH
包装方法:TAPE AND REEL峰值回流温度(摄氏度):260
电源:2/5.5 VProp。Delay @ Nom-Sup:10.5 ns
传播延迟(tpd):10.5 ns认证状态:Not Qualified
座面最大高度:1.45 mm子类别:Bus Driver/Transceivers
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:1.625 mmBase Number Matches:1

74V2G241STR 数据手册

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74V2G241  
DUAL BUS BUFFER NON INVERTED (3-STATE)  
HIGH SPEED: t = 3.8ns (TYP.) at V = 5V  
PD CC  
LOW POWER DISSIPATION:  
I
= 1µA(MAX.) at T = 25°C  
CC  
A
HIGH NOISE IMMUNITY:  
= V = 28% V (MIN.)  
POWER DOWN PROTECTION ON INPUTS  
AND OUTPUTS  
V
NIH  
NIL  
CC  
SOT23-8L  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 8mA (MIN) at V = 4.5V  
OH  
OL  
CC  
BALANCED PROPAGATION DELAYS:  
ORDER CODES  
PACKAGE  
t
t
PLH  
PHL  
T & R  
OPERATING VOLTAGE RANGE:  
(OPR) = 2V to 5.5V  
SOT23-8L  
74V2G241STR  
V
CC  
IMPROVED LATCH-UP IMMUNITY  
inputs with no regard to the supply voltage. This  
device can be used to interface 5V to 3V systems  
and it is ideal for portable applications like  
personal digital assistant, camcorder and all  
battery-powered equipment.  
All inputs and outputs are equipped with  
protection circuits against static discharge, giving  
them ESD immunity and transient excess voltage.  
DESCRIPTION  
The 74V2G241 is an advanced high-speed CMOS  
DUAL BUS BUFFER NON INVERTER fabricated  
with sub-micron silicon gate and double-layer  
metal wiring C MOS technology.  
Power down protection is provided on all inputs  
and outputs and 0 to 7V can be accepted on  
2
PIN CONNECTION AND IEC LOGIC SYMBOLS  
June 2003  
1/9  

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