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74V2G70CTR PDF预览

74V2G70CTR

更新时间: 2024-02-04 07:50:30
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 栅极触发器逻辑集成电路光电二极管
页数 文件大小 规格书
13页 283K
描述
SINGLE D-TYPE FLIP FLOP WITH PRESET AND CLEAR

74V2G70CTR 技术参数

生命周期:Obsolete零件包装代码:SC-70
包装说明:SOT-323, 8 PIN针数:8
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.84Is Samacsys:N
系列:74VJESD-30 代码:R-PDSO-G8
长度:2 mm负载电容(CL):50 pF
逻辑集成电路类型:BUFFER最大I(ol):0.004 A
功能数量:3输入次数:1
端子数量:8最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP8,.09,20
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法:TAPE AND REEL电源:2/5.5 V
Prop。Delay @ Nom-Sup:10.5 ns传播延迟(tpd):10.5 ns
认证状态:Not Qualified施密特触发器:NO
座面最大高度:1.1 mm子类别:Gates
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子形式:GULL WING端子节距:0.5 mm
端子位置:DUAL宽度:1.25 mm
Base Number Matches:1

74V2G70CTR 数据手册

 浏览型号74V2G70CTR的Datasheet PDF文件第2页浏览型号74V2G70CTR的Datasheet PDF文件第3页浏览型号74V2G70CTR的Datasheet PDF文件第4页浏览型号74V2G70CTR的Datasheet PDF文件第5页浏览型号74V2G70CTR的Datasheet PDF文件第6页浏览型号74V2G70CTR的Datasheet PDF文件第7页 
74V2G74  
SINGLE D-TYPE FLIP FLOP WITH PRESET AND CLEAR  
HIGH SPEED:  
= 170 MHz (TYP.) at V = 5V  
f
MAX  
CC  
LOW POWER DISSIPATION:  
= 1 µA (MAX.) at T =25°C  
I
CC  
A
HIGH NOISE IMMUNITY:  
= V = 28% V (MIN.)  
V
NIH  
NIL  
CC  
SOT23-8L  
SOT323-8L  
T & R  
POWER DOWN PROTECTION ON INPUTS  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 8 mA (MIN)  
OH  
OL  
BALANCED PROPAGATION DELAYS:  
ORDER CODES  
t
t
PLH  
PHL  
PACKAGE  
OPERATING VOLTAGE RANGE:  
(OPR) = 2V to 5.5V  
SOT23-8L  
74V2G70STR  
74V2G70CTR  
V
CC  
SOT323-8L  
FUNCTION COMPATIBLE WITH  
74 SERIES 74  
IMPROVED LATCH-UP IMMUNITY  
CLEAR and PRESET are independent of the  
clock and accomplished by a low setting on the  
appropriate input.  
DESCRIPTION  
Power down protection is provided on all inputs  
and 0 to 7V can be accepted on inputs with no  
regard to the supply voltage. This device can be  
used to interface 5V to 3V.  
The 74V2G74 is an advanced high-speed CMOS  
SINGLE D-TYPE FLIP FLOP WITH PRESET  
AND CLEAR fabricated with sub-micron silicon  
2
gate and double-layer metal wiring C MOS  
All inputs and outputs are equipped with  
protection circuits against static discharge, giving  
them ESD immunity and transient excess voltage.  
tecnology.  
A signal on the D INPUT is transfered to the Q and  
Q OUTPUTS during the positive going transition  
of the clock pulse.  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
December 2001  
1/13  

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