Datasheet > 74V2G125CTR

74V2G125CTR

更新时间： 2024-11-03 23:24:35

品牌	Logo	应用领域
其他 - ETC		驱动
页数	文件大小	规格书
11页	79K
描述
BUFFER/DRIVER\|DUAL\|1-BIT\|CMOS\|TSSOP\|8PIN\|PLASTIC

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中文翻译

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数据手册

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74V2G125CTR 数据手册

74V2G125

DUAL BUS BUFFER (3-STATE)

■

HIGH SPEED: t = 3.8ns (TYP.) at V = 5V

PD CC

LOW POWER DISSIPATION:

= 1µA(MAX.) at T =25°C

■

HIGH NOISE IMMUNITY:

= V = 28% V (MIN.)

POWER DOWN PROTECTION ON INPUTS

AND OUTPUTS

NIH

NIL

SOT23-8L

SOT323-8L

T & R

SYMMETRICAL OUTPUT IMPEDANCE:

|I | = I = 8mA (MIN) at V = 4.5V

BALANCED PROPAGATION DELAYS:

ORDER CODES

PLH

PHL

PACKAGE

OPERATING VOLTAGE RANGE:

(OPR) = 2V to 5.5V

SOT23-8L

74V2G125STR

74V2G125CTR

SOT323-8L

IMPROVED LATCH-UP IMMUNITY

DESCRIPTION

The 74V2G125 is an advanced high-speed CMOS

DUAL BUS BUFFER fabricated with sub-micron

This device can be used to interface 5V to 3V

systems and it is ideal for portable applications

like personal digital assistant, camcorder and all

battery-powered equipment.

silicon gate and double-layer metal wiring C MOS

tecnology.

All inputs and outputs are equipped with

protection circuits against static discharge, giving

them ESD immunity and transient excess voltage.

3-STATE control input nG has to be set HIGH to

place the output into the high impedance state.

Power down protection is provided on all inputs

and outputs and 0 to 7V can be accepted on

inputs with no regard to the supply voltage.

PIN CONNECTION AND IEC LOGIC SYMBOLS

November 2001

1/11

12 3 4 5 6 7...11

中文翻译

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