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74V2G125STR PDF预览

74V2G125STR

更新时间: 2024-09-30 21:55:43
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 总线驱动器总线收发器逻辑集成电路光电二极管
页数 文件大小 规格书
9页 160K
描述
DUAL BUS BUFFER (3-STATE)

74V2G125STR 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SOT-23
包装说明:LSSOP, TSSOP8,.1针数:8
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.83Is Samacsys:N
控制类型:ENABLE LOW系列:74V
JESD-30 代码:R-PDSO-G8JESD-609代码:e3
长度:2.9 mm逻辑集成电路类型:BUS DRIVER
最大I(ol):0.004 A湿度敏感等级:1
位数:1功能数量:2
端口数量:2端子数量:8
最高工作温度:125 °C最低工作温度:-55 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:LSSOP
封装等效代码:TSSOP8,.1封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, LOW PROFILE, SHRINK PITCH峰值回流温度(摄氏度):260
电源:2/5.5 VProp。Delay @ Nom-Sup:10.5 ns
传播延迟(tpd):10.5 ns认证状态:Not Qualified
座面最大高度:1.45 mm子类别:Bus Driver/Transceivers
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:1.625 mm
Base Number Matches:1

74V2G125STR 数据手册

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74V2G125  
DUAL BUS BUFFER (3-STATE)  
HIGH SPEED: t = 3.8ns (TYP.) at V = 5V  
PD CC  
LOW POWER DISSIPATION:  
I
= 1µA(MAX.) at T = 25°C  
CC  
A
HIGH NOISE IMMUNITY:  
= V = 28% V (MIN.)  
V
NIH  
NIL  
CC  
POWER DOWN PROTECTION ON INPUTS  
AND OUTPUTS  
SOT23-8L  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 8mA (MIN) at V = 4.5V  
OH  
OL  
CC  
ORDER CODES  
BALANCED PROPAGATION DELAYS:  
PACKAGE  
T & R  
t
t
PLH  
PHL  
OPERATING VOLTAGE RANGE:  
(OPR) = 2V to 5.5V  
SOT23-8L  
74V2G125STR  
V
CC  
Power down protection is provided on all inputs  
and outputs and 0 to 7V can be accepted on  
inputs with no regard to the supply voltage.  
This device can be used to interface 5V to 3V  
systems and it is ideal for portable applications  
like personal digital assistant, camcorder and all  
battery-powered equipment.  
All inputs and outputs are equipped with  
protection circuits against static discharge, giving  
them ESD immunity and transient excess voltage.  
IMPROVED LATCH-UP IMMUNITY  
DESCRIPTION  
The 74V2G125 is an advanced high-speed CMOS  
DUAL BUS BUFFER fabricated with sub-micron  
silicon gate and double-layer metal wiring C MOS  
2
technology.  
3-STATE control input nG has to be set HIGH to  
place the output into the high impedance state.  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
June 2003  
1/9  

74V2G125STR 替代型号

型号 品牌 替代类型 描述 数据表
74V2G126STR STMICROELECTRONICS

完全替代

DUAL BUS BUFFER (3-STATE)

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