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74V2G126 PDF预览

74V2G126

更新时间: 2024-11-03 22:41:35
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS /
页数 文件大小 规格书
11页 81K
描述
DUAL BUS BUFFER (3-STATE)

74V2G126 数据手册

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74V2G126  
DUAL BUS BUFFER (3-STATE)  
HIGH SPEED: t = 3.8ns (TYP.) at V = 5V  
PD CC  
LOW POWER DISSIPATION:  
I
= 1µA(MAX.) at T =25°C  
CC  
A
HIGH NOISE IMMUNITY:  
= V = 28% V (MIN.)  
POWER DOWN PROTECTION ON INPUTS  
AND OUTPUTS  
V
NIH  
NIL  
CC  
SOT23-8L  
SOT323-8L  
T & R  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 8mA (MIN) at V = 4.5V  
OH  
OL  
CC  
BALANCED PROPAGATION DELAYS:  
ORDER CODES  
t
t
PLH  
PHL  
PACKAGE  
OPERATING VOLTAGE RANGE:  
(OPR) = 2V to 5.5V  
SOT23-8L  
74V2G126STR  
74V2G126CTR  
V
CC  
SOT323-8L  
IMPROVED LATCH-UP IMMUNITY  
DESCRIPTION  
The 74V2G126 is an advanced high-speed CMOS  
DUAL BUS BUFFER fabricated with sub-micron  
silicon gate and double-layer metal wiring C MOS  
tecnology.  
inputs with no regard to the supply voltage. This  
device can be used to interface 5V to 3V systems  
and it is ideal for portable applications like  
personal digital assistant, camcorder and all  
battery-powered equipment.  
2
All inputs and outputs are equipped with  
protection circuits against static discharge, giving  
them ESD immunity and transient excess voltage.  
3-STATE control input nG has to be set LOW to  
place the output into the high impedance state.  
Power down protection is provided on all inputs  
and outputs and 0 to 7V can be accepted on  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
November 2001  
1/11  

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