74V2G125

更新时间： 2024-09-30 21:55:43

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		/
页数	文件大小	规格书
9页	160K
描述
DUAL BUS BUFFER (3-STATE)

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中文翻译

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数据手册

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74V2G125 数据手册

74V2G125

DUAL BUS BUFFER (3-STATE)

■

HIGH SPEED: t = 3.8ns (TYP.) at V = 5V

PD CC

LOW POWER DISSIPATION:

= 1µA(MAX.) at T = 25°C

■

HIGH NOISE IMMUNITY:

= V = 28% V (MIN.)

NIH

NIL

POWER DOWN PROTECTION ON INPUTS

AND OUTPUTS

SOT23-8L

SYMMETRICAL OUTPUT IMPEDANCE:

|I | = I = 8mA (MIN) at V = 4.5V

ORDER CODES

BALANCED PROPAGATION DELAYS:

PACKAGE

T & R

PLH

PHL

OPERATING VOLTAGE RANGE:

(OPR) = 2V to 5.5V

SOT23-8L

74V2G125STR

Power down protection is provided on all inputs

and outputs and 0 to 7V can be accepted on

inputs with no regard to the supply voltage.

This device can be used to interface 5V to 3V

systems and it is ideal for portable applications

like personal digital assistant, camcorder and all

battery-powered equipment.

All inputs and outputs are equipped with

protection circuits against static discharge, giving

them ESD immunity and transient excess voltage.

IMPROVED LATCH-UP IMMUNITY

DESCRIPTION

The 74V2G125 is an advanced high-speed CMOS

DUAL BUS BUFFER fabricated with sub-micron

silicon gate and double-layer metal wiring C MOS

technology.

3-STATE control input nG has to be set HIGH to

place the output into the high impedance state.

PIN CONNECTION AND IEC LOGIC SYMBOLS

June 2003

1/9

12 3 4 5 6 7...9

中文翻译

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