Datasheet > 74V2G05

74V2G05

更新时间： 2024-10-01 03:21:59

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		/
页数	文件大小	规格书
7页	131K
描述
TRIPLE INVERTER

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中文翻译

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数据手册

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74V2G05 数据手册

74V2G05

TRIPLE INVERTER (OPEN DRAIN)

■

HIGH SPEED: t = 3.7ns (TYP.) at V = 5V

PD CC

LOW POWER DISSIPATION:

= 1µA(MAX.) at T = 25°C

■

HIGH NOISE IMMUNITY:

= V = 28% V (MIN.)

NIH

NIL

■

POWER DOWN PROTECTION ON INPUT

OPERATING VOLTAGE RANGE:

SOT23-8L

(OPR) = 2V to 5.5V

■

IMPROVED LATCH-UP IMMUNITY

ORDER CODES

DESCRIPTION

PACKAGE

T & R

The 74V2G05 is an advanced high-speed CMOS

TRIPLE INVERTER (OPEN DRAIN) fabricated

with sub-micron silicon gate and double-layer

SOT23-8L

74V2G05STR

Power down protection is provided on input and 0

to 7V can be accepted on input with no regard to

the supply voltage. This device can be used to

interface 5V to 3V.

metal wiring C MOS technology.

The internal circuit is composed of 3 stages

including buffer output, which provide high noise

immunity and stable output.

PIN CONNECTION AND IEC LOGIC SYMBOLS

June 2003

1/7

12 3 4 5 6 7

中文翻译

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74V2G07	STMICROELECTRONICS	获取价格	TRIPLE BUFFER (OPEN DRAIN)
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74V2G07STR	STMICROELECTRONICS	获取价格	TRIPLE BUFFER (OPEN DRAIN)
74V2G08	STMICROELECTRONICS	获取价格	DUAL 2-INPUT AND GATE
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74V2G08STR	STMICROELECTRONICS	获取价格	DUAL 2-INPUT AND GATE
74V2G125	STMICROELECTRONICS	获取价格	DUAL BUS BUFFER (3-STATE)
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