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74V2G07 PDF预览

74V2G07

更新时间: 2024-11-03 22:16:47
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS /
页数 文件大小 规格书
9页 193K
描述
TRIPLE BUFFER (OPEN DRAIN)

74V2G07 数据手册

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74V2G07  
TRIPLE BUFFER (OPEN DRAIN)  
PRELIMINARY DATA  
HIGH SPEED: t =3.7ns (TYP.) at V = 5V  
PD CC  
LOW POWER DISSIPATION:  
I
= 1µA(MAX.) at T =25°C  
CC  
A
HIGH NOISE IMMUNITY:  
= V = 28% V (MIN.)  
V
NIH  
NIL  
CC  
POWER DOWN PROTECTION ON INPUT  
SOT23-8L  
SOT323-8L  
T & R  
OPERATING VOLTAGE RANGE:  
V
(OPR) = 2V to 5.5V  
CC  
IMPROVED LATCH-UP IMMUNITY  
ORDER CODES  
PACKAGE  
DESCRIPTION  
SOT23-8L  
74V2G07STR  
74V2G07CTR  
The 74V2G07 is an advanced high-speed CMOS  
TRIPLE BUFFER (OPEN DRAIN) fabricated with  
sub-micron silicon gate and double-layer metal  
SOT323-8L  
2
wiring C MOS technology.  
Power down protection is provided on input and 0  
to 7V can be accepted on input with no regard to  
the supply voltage. This device can be used to  
interface 5V to 3V.  
The internal circuit is composed of 2 stages  
including buffer output, which provide high noise  
immunity and stable output.  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
November 2001  
1/9  
This is preliminary information on a new product now in development are or undergoing evaluation. Details subject to change without notice.  

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