Datasheet > 74V2G04

74V2G04

更新时间： 2024-11-03 23:15:55

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		/
页数	文件大小	规格书
7页	128K
描述
TRIPLE INVERTER

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中文翻译

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数据手册

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74V2G04 数据手册

74V2G04

TRIPLE INVERTER

■

HIGH SPEED: t = 3.8ns (TYP.) at V = 5V

PD CC

LOW POWER DISSIPATION:

= 1µA(MAX.) at T = 25°C

■

HIGH NOISE IMMUNITY:

= V = 28% V (MIN.)

NIH

NIL

■

POWER DOWN PROTECTION ON INPUT

SOT23-8L

SYMMETRICAL OUTPUT IMPEDANCE:

|I | = I = 8mA (MIN) at V = 4.5V

■

BALANCED PROPAGATION DELAYS:

ORDER CODES

PACKAGE

PLH

PHL

T & R

OPERATING VOLTAGE RANGE:

(OPR) = 2V to 5.5V

SOT23-8L

74V2G04STR

IMPROVED LATCH-UP IMMUNITY

The internal circuit is composed of 3 stages

including buffer output, which provide high noise

immunity and stable output.

DESCRIPTION

The 74V2G04 is an advanced high-speed CMOS

TRIPLE INVERTER fabricated with sub-micron

silicon gate and double-layer metal wiring C MOS

Power down protection is provided on input and 0

to 7V can be accepted on input with no regard to

the supply voltage. This device can be used to

interface 5V to 3V.

technology.

PIN CONNECTION AND IEC LOGIC SYMBOLS

June 2003

1/7

12 3 4 5 6 7

中文翻译

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