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STP3052D

更新时间： 2024-11-24 17:15:23

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STP3052D 数据手册

STP3052D

P Channel Enhancement Mode MOSFET

25.0A

ꢀ

DESCRIPTION

STP3052D is the PꢀChannel logic enhancement mode power field effect transistor

which is produced using high cell density, DMOS trench technology.

This high density process is especially tailored to minimize onꢀstate resistance. These

devices are particularly suited for low voltage application. Such as DC/DC converter

and Desktop computer power management.

The package is universally preferred for commercial industrial surface mount

applications.

FEATURE

PIN CONFIGURATION (D-PAK)

ꢀ

ꢀ30V/ꢀ25.0A, R_DS(ON)= 45mꢁ (Typ.)

TO-252

TO-251

@VGS = ꢀ10V

ꢀ30V/ꢀ16.0A, R_DS(ON)= 78mꢁ

@VGS =ꢀ5.0V

Super high density cell design for

extremely low R_DS(ON)

Exceptional onꢀresistance and

maximum DC current capability

TOꢀ252,TOꢀ251 package design

PART MARKING

Y: Year Code A: Process Code

STANSON TECHNOLOGY

120 Bentley Square, Mountain View, Ca 94040 USA

www.stansontech.com

STP3052D 2009. V1

12 3 4 5 6

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