FDG313N_NL

更新时间： 2024-11-18 13:07:47

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		/
页数	文件大小	规格书
8页	714K
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FDG313N_NL 数据手册

July 2000

FDG313N

Digital FET, N-Channel

General Description

Features

This N-Channel enhancement mode field effect

transistor is produced using Fairchild's proprietary, high

cell density, DMOS technology. This very high density

process is especially tailored to minimize on-state

resistance. This device has been designed especially

for low voltage applications as a replacement for

bipolar digital transistor and small signal MOSFET.

• 0.95 A, 25 V. R_DS(on)= 0.45 Ω @ V_GS= 4.5 V

R_DS(on)= 0.60 Ω @ V_GS= 2.7 V.

• Low gate charge (1.64 nC typical)

• Very low level gate drive requirements allowing direct

operation in 3V circuits (V_GS(th)< 1.5V).

Applications

• Load switch

• Gate-Source Zener for ESD ruggedness

(>6kV Human Body Model).

• Battery protection

• Power management

• Compact industry standard SC70-6 surface mount

package.

SC70-6

T_A= 25°C unless otherwise noted

Absolute Maximum Ratings

Symbol

V_DSS

Parameter

FDG313N

Units

Drain-Source Voltage

Gate-Source Voltage

V_GSS

(Note 1a)

I_D

Drain Current - Continuous

- Pulsed

0.95

P_D

Power Dissipation for Single Operation

0.75

0.55

(Note 1b)

(Note 1c)

0.48

T_J, T_stg

ESD

Operating and Storage Junction Temperature Range

-55 to +150

Electrostatic Discharge Rating MIL-STD-883D

Human Body Model (100pf / 1500 Ohm)

Thermal Characteristics

(Note 1c)

θ^JA

Thermal Resistance, Junction-to-Ambient

260

C/W

Package Outlines and Ordering Information

Device Marking

Device

Reel Size

Tape Width

Quantity

3000 units

FDG313N

7’’

8mm

1998 Fairchild Semiconductor Corporation

FDG313N Rev. C

12 3 4 5 6 7 8

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