FDC634P-G

更新时间： 2024-02-12 14:03:24

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		晶体晶体管场效应晶体管
页数	文件大小	规格书
4页	74K
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FDC634P-G 数据手册

November 1997

FDC634P

P-Channel Enhancement Mode Field Effect Transistor

General Description

Features

-3.5 A, -20 V. R_DS(ON)= 0.080 W @ V_GS= -4.5 V

These P-Channel logic level enhancement mode power

field effect transistors are produced using Fairchild's

proprietary, high cell density, DMOS technology. This very

high density process is especially tailored to minimize

on-state resistance. These devices are particularly suited

for low voltage applications such as cellular phone and

notebook computer power management and other battery

powered circuits where high-side switching, and low in-line

power loss are needed in a very small outline surface

mount package.

R_DS(ON)= 0.110 W @ V_GS= -2.5 V.

SuperSOT^TM-6 package design using copper lead frame for

superior thermal and electrical capabilities.

High density cell design for extremely low R_DS(ON)

Exceptional on-resistance and maximum DC current

capability.

SuperSOT^TM-6

SuperSOT^TM-8

SOIC-16

SOT-223

SO-8

SOT-23

SuperSOT^TM-6

Absolute Maximum RatingsT_A= 25°C unless otherwise note

Symbol Parameter

FDC634P

Units

Drain-Source Voltage

-20

±8

V_DSS

V_GSS

I_D

Gate-Source Voltage - Continuous

Drain Current - Continuous

- Pulsed

(Note 1a)

-3.5

-11

P_D

Maximum Power Dissipation

(Note 1a)

(Note 1b)

1.6

0.8

T_J,T_STGOperating and Storage Temperature Range

-55 to 150

°C

THERMAL CHARACTERISTICS

R_qJA

R_qJC

Thermal Resistance, Junction-to-Ambient

Thermal Resistance, Junction-to-Case

(Note 1a)

(Note 1)

°C/W

FDC634P Rev.C

12 3 4

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