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STP2301_V1 PDF预览

STP2301_V1

更新时间: 2024-11-26 12:24:19
品牌 Logo 应用领域
其他 - ETC /
页数 文件大小 规格书
7页 371K
描述
P Channel Enhancement Mode MOSFET

STP2301_V1 数据手册

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STP2301  
P Channel Enhancement Mode MOSFET  
-2.8A  
DESCRIPTION  
The STP2301 is the P-Channel logic enhancement mode power field effect transistor is  
produced using high cell density, DMOS trench technology.  
This high density process is especially tailored to minimize on-state resistance.  
These devices are particularly suited for low voltage application such as cellular phone  
and notebook computer power management and other batter powered circuits, and  
low in-line power loss are needed in a very small outline surface mount package.  
FEATURE  
PIN CONFIGURATION  
SOT-23  
-20V/-2.8A, RDS(ON) = 90m-ohm (Typ.)  
@VGS = -4.5V  
-20V/-2.0A, RDS(ON) = 110m-ohm  
@VGS = -2.5V  
Super high density cell design for  
extremely low RDS(ON)  
Exceptional on-resistance and maximum  
DC current capability  
SOT-23 package design  
3
D
G
1
S
2
1.Gate 2.Source 3.Drain  
PART MARKING  
SOT-23  
3
S01YA  
1
2
Y: Year Code A: Process Code  
1
120 Bentley Square, Mountain View, Ca 94040 USA  
www.stansontech.com  
STP2301 2007. V1  

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