Datasheet > STP2301_V1

STP2301_V1

更新时间： 2024-02-13 09:29:06

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描述
P Channel Enhancement Mode MOSFET

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STP2301_V1 数据手册

STP2301

P Channel Enhancement Mode MOSFET

-2.8A

DESCRIPTION

The STP2301 is the P-Channel logic enhancement mode power field effect transistor is

produced using high cell density, DMOS trench technology.

This high density process is especially tailored to minimize on-state resistance.

These devices are particularly suited for low voltage application such as cellular phone

and notebook computer power management and other batter powered circuits, and

low in-line power loss are needed in a very small outline surface mount package.

FEATURE

PIN CONFIGURATION

SOT-23

ꢀ

-20V/-2.8A, R_DS(ON)= 90m-ohm (Typ.)

@VGS = -4.5V

-20V/-2.0A, R_DS(ON)= 110m-ohm

@VGS = -2.5V

Super high density cell design for

extremely low R_DS(ON)

Exceptional on-resistance and maximum

DC current capability

SOT-23 package design

1.Gate 2.Source 3.Drain

PART MARKING

SOT-23

S01YA

Y: Year Code A: Process Code

120 Bentley Square, Mountain View, Ca 94040 USA

www.stansontech.com

STP2301 2007. V1

12 3 4 5 6 7

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