Datasheet > PSMN8R0-30YL

PSMN8R0-30YL

更新时间： 2024-09-16 10:00:23

品牌	Logo	应用领域
恩智浦 - NXP		晶体晶体管开关脉冲
页数	文件大小	规格书
14页	328K
描述
N-channel 8.3 mΩ 30 V TrenchMOS logic level FET in LFPAK

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PSMN8R0-30YL 数据手册

PSMN8R0-30YL

LFP

N-channel 8.3 mΩ 30 V TrenchMOS logic level FET in LFPAK

Rev. 2 — 16 May 2011

Product data sheet

1. Product profile

1.1 General description

Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic

package using TrenchMOS technology. This product is designed and qualified for use in

industrial and communications applications.

1.2 Features and benefits

High efficiency due to low switching

Suitable for logic level gate drive

and conduction losses

sources

1.3 Applications

Class-D amplifiers

Motor control

DC-to-DC converters

Server power supplies

1.4 Quick reference data

Table 1.

Quick reference data

Conditions

Symbol Parameter

Min Typ Max Unit

V_DS

I_D

drain-source

voltage

T_j≥ 25 °C; T_j≤ 175 °C

drain current

T_mb= 25 °C; V_GS= 10 V;

see Figure 1

P_tot

total power

dissipation

T_mb= 25 °C; see Figure 2

Static characteristics

R_DSon

drain-source

V_GS= 10 V; I_D= 15 A; T_j= 25 °C

6.9

8.3

mΩ

on-state resistance

Dynamic characteristics

Q_GD

gate-drain charge

V_GS= 10 V; I_D= 45 A; V_DS= 15 V;

see Figure 14; see Figure 15

Q_G(tot)

total gate charge

V_GS= 4.5 V; I_D= 45 A; V_DS= 15 V;

see Figure 14; see Figure 15

Avalanche ruggedness

E_DS(AL)Snon-repetitive

drain-source

_GS= 10 V; T_j(init)= 25 °C;

I_D= 62 A; V_sup≤ 30 V;R_GS= 50 Ω;

avalanche energy

unclamped

12 3 4 5 6 7...14

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