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PSMN8R0-30YL_1105 PDF预览

PSMN8R0-30YL_1105

更新时间: 2024-11-21 10:00:23
品牌 Logo 应用领域
恩智浦 - NXP /
页数 文件大小 规格书
14页 328K
描述
N-channel 8.3 mΩ 30 V TrenchMOS logic level FET in LFPAK

PSMN8R0-30YL_1105 数据手册

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PSMN8R0-30YL  
AK  
LFP  
N-channel 8.3 m30 V TrenchMOS logic level FET in LFPAK  
Rev. 2 — 16 May 2011  
Product data sheet  
1. Product profile  
1.1 General description  
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic  
package using TrenchMOS technology. This product is designed and qualified for use in  
industrial and communications applications.  
1.2 Features and benefits  
„ High efficiency due to low switching  
„ Suitable for logic level gate drive  
and conduction losses  
sources  
1.3 Applications  
„ Class-D amplifiers  
„ Motor control  
„ DC-to-DC converters  
„ Server power supplies  
1.4 Quick reference data  
Table 1.  
Quick reference data  
Conditions  
Symbol Parameter  
Min Typ Max Unit  
VDS  
ID  
drain-source  
voltage  
Tj 25 °C; Tj 175 °C  
-
-
-
-
-
-
30  
62  
56  
V
drain current  
Tmb = 25 °C; VGS = 10 V;  
see Figure 1  
A
Ptot  
total power  
dissipation  
Tmb = 25 °C; see Figure 2  
W
Static characteristics  
RDSon  
drain-source  
VGS = 10 V; ID = 15 A; Tj = 25 °C  
-
6.9  
8.3  
mΩ  
on-state resistance  
Dynamic characteristics  
QGD  
gate-drain charge  
VGS = 10 V; ID = 45 A; VDS = 15 V;  
see Figure 14; see Figure 15  
-
-
4
9
-
-
nC  
nC  
QG(tot)  
total gate charge  
VGS = 4.5 V; ID = 45 A; VDS = 15 V;  
see Figure 14; see Figure 15  
Avalanche ruggedness  
EDS(AL)S non-repetitive  
drain-source  
V
GS = 10 V; Tj(init) = 25 °C;  
-
-
21  
mJ  
ID = 62 A; Vsup 30 V;RGS = 50 ;  
avalanche energy  
unclamped  

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