Datasheet > NTMD5836NLR2G

NTMD5836NLR2G

更新时间： 2024-11-20 10:30:19

品牌	Logo	应用领域
安森美 - ONSEMI		栅极
页数	文件大小	规格书
10页	131K
描述
Power MOSFET 40 V, Dual N?Channel, SOIC?8 Optimized Gate Charge

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NTMD5836NLR2G 数据手册

NTMD5836NL

Power MOSFET

40 V, Dual N−Channel, SOIC−8

Features

• Asymmetrical N Channels

http://onsemi.com

• Low R

DS(on)

• Low Capacitance

• Optimized Gate Charge

N−Channel 1

N−Channel 2

• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS

Compliant

Max

(Notes 1 and 2)

Max

DS(on)

(BR)DSS

Channel 1

Channel 2

40 V

11 A

12 mW @ 10 V

16 mW @ 4.5 V

25 mW @ 10 V

30.8 mW @ 4.5 V

40 V

6.5 A

MARKING DIAGRAM*

AND PIN ASSIGNMENT

1. Surface−mounted on FR4 board using 1 in sq pad size (Cu area = 1.127 in

sq [2 oz] including traces)

2. Only selected channel is been powered

D1 D1 D2 D2

1W applied on channel 1: T = 1 W * 85°C/W + 25°C = 110°C

5836NL

AYWW G

SOIC−8

CASE 751

S1 G1 S2 G2

= Assembly Location

= Year

= Work Week

= Pb−Free Package

(Note: Microdot may be in either location)

ORDERING INFORMATION

†

Device

Package

Shipping

NTMD5836NLR2G SOIC−8

(Pb−Free)

2500 /

Tape & Reel

†For information on tape and reel specifications,

including part orientation and tape sizes, please

refer to our Tape and Reel Packaging Specifications

Brochure, BRD8011/D

Publication Order Number:

March, 2011 − Rev. 0

NTMD5836NL/D

12 3 4 5 6 7...10

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