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MMDF2C02E PDF预览

MMDF2C02E

更新时间： 2024-11-17 22:30:03
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 晶体晶体管功率场效应晶体管开关脉冲光电二极管
页数 文件大小 规格书
12页 327K
描述
COMPLEMENTARY DUAL TMOS POWER FET 2.5 AMPERES 25 VOLTS

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中文翻译

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MMDF2C02E 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：SOT包装说明：SMALL OUTLINE, R-PDSO-G8
针数：8Reach Compliance Code：unknown
ECCN代码：EAR99HTS代码：8541.29.00.95
风险等级：5.7Is Samacsys：N
雪崩能效等级（Eas）：245 mJ配置：SEPARATE, 2 ELEMENTS
最小漏源击穿电压：20 V最大漏极电流 (Abs) (ID)：2.2 A
最大漏极电流 (ID)：2 A最大漏源导通电阻：0.2 Ω
FET 技术：METAL-OXIDE SEMICONDUCTORJESD-30 代码：R-PDSO-G8
JESD-609代码：e0元件数量：2
端子数量：8工作模式：ENHANCEMENT MODE
最高工作温度：150 °C封装主体材料：PLASTIC/EPOXY
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
峰值回流温度（摄氏度）：NOT SPECIFIED极性/信道类型：N-CHANNEL AND P-CHANNEL
最大功率耗散 (Abs)：1.5 W最大脉冲漏极电流 (IDM)：18 A
认证状态：Not Qualified子类别：Other Transistors
表面贴装：YES端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED晶体管应用：SWITCHING
晶体管元件材料：SILICONBase Number Matches：1

MMDF2C02E 数据手册

 浏览型号MMDF2C02E的Datasheet PDF文件第2页浏览型号MMDF2C02E的Datasheet PDF文件第3页浏览型号MMDF2C02E的Datasheet PDF文件第4页浏览型号MMDF2C02E的Datasheet PDF文件第5页浏览型号MMDF2C02E的Datasheet PDF文件第6页浏览型号MMDF2C02E的Datasheet PDF文件第7页 
Order this document  
by MMDF2C02E/D  
SEMICONDUCTOR TECHNICAL DATA  
Medium Power Surface Mount Products  
COMPLEMENTARY  
DUAL TMOS POWER FET  
2.5 AMPERES  
MiniMOS devices are an advanced series of power MOSFETs  
which utilize Motorola’s TMOS process. These miniature surface  
25 VOLTS  
mount MOSFETs feature ultra low R  
and true logic level  
DS(on)  
R
= 0.100 OHM  
performance. They are capable of withstanding high energy in the  
avalanche and commutation modes and the drain–to–source diode  
has a low reverse recovery time. MiniMOS devices are designed  
for use in low voltage, high speed switching applications where  
power efficiency is important. Typical applications are dc–dc  
converters, and power management in portable and battery  
powered products such as computers, printers, cellular and  
cordless phones. They can also be used for low voltage motor  
controls in mass storage products such as disk drives and tape  
drives. The avalanche energy is specified to eliminate the  
guesswork in designs where inductive loads are switched and offer  
additional safety margin against unexpected voltage transients.  
DS(on)  
(N–CHANNEL)  
= 0.25 OHM  
R
DS(on)  
(P–CHANNEL)  
D
N–Channel  
G
CASE 751–05, Style 14  
SO–8  
S
•
Ultra Low R  
Battery Life  
Provides Higher Efficiency and Extends  
DS(on)  
D
P–Channel  
•
•
•
•
•
•
Logic Level Gate Drive — Can Be Driven by Logic ICs  
Miniature SO–8 Surface Mount Package — Saves Board Space  
Diode Is Characterized for Use In Bridge Circuits  
Diode Exhibits High Speed, with Soft Recovery  
Avalanche Energy Specified  
1
2
3
4
8
7
6
5
N–Drain  
N–Drain  
P–Drain  
P–Drain  
N–Source  
N–Gate  
P–Source  
P–Gate  
G
Mounting Information for SO–8 Package Provided  
Top View  
S
(1)  
MAXIMUM RATINGS (T = 25°C unless otherwise noted)  
J
Rating  
Drain–to–Source Voltage  
Symbol  
Value  
25  
Unit  
Vdc  
Vdc  
Adc  
V
DSS  
Gate–to–Source Voltage  
V
GS  
± 20  
Drain Current — Continuous  
N–Channel  
P–Channel  
N–Channel  
P–Channel  
I
D
3.6  
2.5  
18  
— Pulsed  
I
DM  
13  
Operating and Storage Temperature Range  
(2)  
T
J
and T  
stg  
– 55 to 150  
2.0  
°C  
Watts  
mJ  
Total Power Dissipation @ T = 25°C  
P
D
A
Single Pulse Drain–to–Source Avalanche Energy — Starting T = 25°C  
E
AS  
J
(V  
DD  
(V  
DD  
= 20 V, V  
= 20 V, V  
= 10 V, Peak I = 9.0 A, L = 6.0 mH, R = 25 Ω)  
N–Channel  
P–Channel  
245  
245  
GS  
GS  
L
G
G
= 10 V, Peak I = 7.0 A, L = 10 mH, R = 25 Ω)  
L
(2)  
Thermal Resistance — Junction to Ambient  
R
62.5  
260  
°C/W  
°C  
θJA  
Maximum Lead Temperature for Soldering, 0.0625″ from case. Time in Solder Bath is 10 seconds.  
T
L
DEVICE MARKING  
F2C02  
(1) Negative signs for P–Channel device omitted for clarity.  
(2) Mounted on 2” square FR4 board (1” sq. 2 oz. Cu 0.06” thick single sided) with one die operating, 10 sec. max.  
ORDERING INFORMATION  
Device  
Reel Size  
Tape Width  
Quantity  
MMDF2C02ER2  
13″  
12 mm embossed tape  
2500 units  
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit  
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.  
Designer’s and MiniMOS are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.  
Thermal Clad is a trademark of the Bergquist Company.  
REV 5  
Motorola, Inc. 1996  
1234567...12

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