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MMDF2N06VLR1 PDF预览

MMDF2N06VLR1

更新时间： 2024-09-09 16:16:43
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA /
页数 文件大小 规格书
4页 114K
描述
Small Signal Field-Effect Transistor, 2.5A I(D), 60V, 2-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, MINIATURE, CASE 751-05, SO-8

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MMDF2N06VLR1 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
包装说明：MINIATURE, CASE 751-05, SO-8Reach Compliance Code：unknown
风险等级：5.92其他特性：AVALANCHE ENERGY RATED
配置：SEPARATE, 2 ELEMENTS WITH BUILT-IN DIODE最小漏源击穿电压：60 V
最大漏极电流 (Abs) (ID)：2.5 A最大漏极电流 (ID)：2.5 A
最大漏源导通电阻：0.19 ΩFET 技术：METAL-OXIDE SEMICONDUCTOR
最大反馈电容 (Crss)：50 pFJESD-30 代码：R-PDSO-G8
JESD-609代码：e0元件数量：2
端子数量：8工作模式：ENHANCEMENT MODE
最高工作温度：170 °C封装主体材料：PLASTIC/EPOXY
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
峰值回流温度（摄氏度）：NOT SPECIFIED极性/信道类型：N-CHANNEL
最大功率耗散 (Abs)：2 W认证状态：Not Qualified
子类别：FET General Purpose Power表面贴装：YES
端子面层：Tin/Lead (Sn/Pb)端子形式：GULL WING
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
晶体管应用：SWITCHING晶体管元件材料：SILICON
Base Number Matches：1

MMDF2N06VLR1 数据手册

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Order this document  
by MMDF2N06VL/D  
SEMICONDUCTOR TECHNICAL DATA  
N–Channel Enhancement–Mode Silicon Gate  
DUAL TMOS MOSFET  
2.5 AMPERES  
60 VOLTS  
TMOS V is a new technology designed to achieve an on–resis-  
tance area product about one–half that of standard MOSFETs. This  
new technology more than doubles the present cell density of our  
50 and 60 volt TMOS devices. Just as with our TMOS E–FET  
designs, TMOS V is designed to withstand high energy in the  
avalanche and commutation modes. Designed for low voltage, high  
speed switching applications in power supplies, converters and  
power motor controls, these devices are particularly well suited for  
bridge circuits where diode speed and commutating safe operating  
areas are critical and offer additional safety margin against  
unexpected voltage transients.  
R
= 0.130 OHM  
DS(on)  
TM  
D
CASE 751–05, Style 11  
SO–8  
G
New Features of TMOS V  
•
On–resistance Area Product about One–half that of Standard  
MOSFETs with New Low Voltage, Low R Technology  
S
DS(on)  
Faster Switching than E–FET Predecessors  
•
1
2
3
4
8
7
6
5
Drain–1  
Drain–1  
Drain–2  
Drain–2  
Source–1  
Gate–1  
Features Common to TMOS V and TMOS E–FETS  
•
•
•
•
•
Avalanche Energy Specified  
and V Specified at Elevated Temperature  
Static Parameters are the Same for both TMOS V and TMOS E–FET  
Miniature SO–8 Surface Mount Package – Saves Board Space  
Mounting Information for SO–8 Package Provided  
Source–2  
Gate–2  
I
DSS  
DS(on)  
Top View  
MAXIMUM RATINGS (T = 25°C unless otherwise noted)  
J
Rating  
Symbol  
Value  
60  
Unit  
Vdc  
Vdc  
Vdc  
Adc  
Drain–to–Source Voltage  
V
DSS  
Drain–to–Gate Voltage, (R  
GS  
= 1 MΩ)  
V
DGR  
60  
Gate–to–Source Voltage — Continuous  
Drain Current — Continuous @ T = 25°C  
Drain Current — Continuous @ T = 100°C  
V
GS  
± 15  
I
I
2.5  
0.5  
7.5  
A
A
D
D
Drain Current — Single Pulse (t ≤ 10 µs)  
I
Apk  
W
p
DM  
(1)  
Total Power Dissipation @ T = 25°C  
P
D
2.0  
–55 to 175  
54  
A
Operating and Storage Temperature Range  
T , T  
J stg  
°C  
Single Pulse Drain–to–Source Avalanche Energy — Starting T = 25°C  
E
AS  
mJ  
J
(V  
DD  
= 25 Vdc, V  
GS  
= 5.0 Vdc, Peak I = 3.3 Apk, L = 10 mH, R = 25 Ω)  
L
G
(1)  
Thermal Resistance, Junction to Ambient  
R
62.5  
260  
°C/W  
°C  
θJA  
Maximum Lead Temperature for Soldering Purposes, 0.0625″ from case for 10 seconds  
T
L
DEVICE MARKING  
2N6VL  
(1) Mounted on G10/FR4 glass epoxy board using minimum recommended footprint.  
ORDERING INFORMATION  
Device  
Reel Size  
Tape Width  
Quantity  
500  
MMDF2N06VLR1  
MMDF2N06VLR2  
7″  
12mm embossed tape  
12mm embossed tape  
13″  
2500  
This document contains information on a new product. Specifications and information herein are subject to change without notice.  
E–FET and TMOS V are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.  
Motorola, Inc. 1996  
1234

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