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FDC634 PDF预览

FDC634

更新时间: 2024-11-20 22:49:03
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 晶体晶体管场效应晶体管
页数 文件大小 规格书
4页 74K
描述
P-Channel Enhancement Mode Field Effect Transistor

FDC634 数据手册

 浏览型号FDC634的Datasheet PDF文件第2页浏览型号FDC634的Datasheet PDF文件第3页浏览型号FDC634的Datasheet PDF文件第4页 
November 1997  
FDC634P  
P-Channel Enhancement Mode Field Effect Transistor  
General Description  
Features  
-3.5 A, -20 V. RDS(ON) = 0.080 W @ VGS = -4.5 V  
These P-Channel logic level enhancement mode power  
field effect transistors are produced using Fairchild's  
proprietary, high cell density, DMOS technology. This very  
high density process is especially tailored to minimize  
on-state resistance. These devices are particularly suited  
for low voltage applications such as cellular phone and  
notebook computer power management and other battery  
powered circuits where high-side switching, and low in-line  
power loss are needed in a very small outline surface  
mount package.  
RDS(ON) = 0.110 W @ VGS = -2.5 V.  
SuperSOTTM-6 package design using copper lead frame for  
superior thermal and electrical capabilities.  
High density cell design for extremely low RDS(ON)  
.
Exceptional on-resistance and maximum DC current  
capability.  
SuperSOTTM-6  
SuperSOTTM-8  
SOIC-16  
SOT-223  
SO-8  
SOT-23  
S
1
6
5
4
D
D
2
3
G
D
pin  
1
SuperSOTTM -6  
D
Absolute Maximum RatingsTA = 25°C unless otherwise note  
Symbol Parameter  
FDC634P  
Units  
Drain-Source Voltage  
-20  
±8  
V
V
A
VDSS  
VGSS  
ID  
Gate-Source Voltage - Continuous  
Drain Current - Continuous  
- Pulsed  
(Note 1a)  
-3.5  
-11  
PD  
Maximum Power Dissipation  
(Note 1a)  
(Note 1b)  
1.6  
W
0.8  
TJ,TSTG Operating and Storage Temperature Range  
-55 to 150  
°C  
THERMAL CHARACTERISTICS  
RqJA  
RqJC  
Thermal Resistance, Junction-to-Ambient  
Thermal Resistance, Junction-to-Case  
(Note 1a)  
(Note 1)  
78  
30  
°C/W  
°C/W  
© 1997 Fairchild Semiconductor Corporation  
FDC634P Rev.C  

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