74V1T80

更新时间： 2024-11-04 08:04:43

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		触发器
页数	文件大小	规格书
9页	117K
描述
SINGLE POSITIVE EDGE TRIGGERED D-TYPE FLIP-FLOP

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中文翻译

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数据手册

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74V1T80 数据手册

74V1T80

SINGLE POSITIVE EDGE TRIGGERED

D-TYPE FLIP-FLOP

■

HIGH SPEED:

= 180MHz (TYP.) at V = 5V

MAX

LOW POWER DISSIPATION:

= 1µA(MAX.) at T =25°C

COMPATIBLE WITH TTL OUTPUTS:

= 2V (MIN), V = 0.8V (MAX)

SOT23-5L

SOT323-5L

T & R

■

POWER DOWN PROTECTION ON INPUTS

SYMMETRICAL OUTPUT IMPEDANCE:

|I | = I = 8mA (MIN) at V = 4.5V

■

BALANCED PROPAGATION DELAYS:

ORDER CODES

PLH

PHL

PACKAGE

OPERATING VOLTAGE RANGE:

(OPR) = 4.5V to 5.5V

SOT23-5L

74V1T80STR

74V1T80CTR

SOT323-5L

IMPROVED LATCH-UP IMMUNITY

DESCRIPTION

The 74V1T80 is an advanced high-speed CMOS

SINGLE POSITIVE EDGE TRIGGERED D-TYPE

Following the hold time interval, data at the D input

can be changed without affecting the level at the

output. Power down protection is provided on

input and 0 to 7V can be accepted on input with no

regard to the supply voltage. This device can be

used to interface 5V to 3V.

FLIP-FLOP

WITH

INVERTED

OUTPUT

fabricated with sub-micron silicon gate and

double-layer metal wiring C MOS technology. it is

designed to operate from 4.5V to 5.5V, making

this device ideal for portable applications.

This D-Type flip-flop is controlled by a clock input

(CK). On the positive transition of the clock, the Q

output will be set to the logic inverted state that

was setup at the D input.

It’s available in the commercial temperature

range. All inputs and output are equipped with

protection circuits against static discharge, giving

them ESD immunity and transient excess voltage.

PIN CONNECTION AND IEC LOGIC SYMBOLS

April 2004

1/9

12 3 4 5 6 7...9

中文翻译

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