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74V2G00

更新时间： 2024-11-03 22:11:47

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		输入元件
页数	文件大小	规格书
6页	46K
描述
DUAL 2-INPUT NAND GATE

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中文翻译

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74V2G00 数据手册

74V2G00

DUAL 2-INPUT NAND GATE

■

HIGH SPEED:t_PD=3.7ns (TYP.) atV_CC= 5V

LOW POWER DISSIPATION:

_CC=1 µA (MAX.) at T_A=25 ^oC

■

HIGH NOISEIMMUNITY:

_NIH= V_NIL=28% V_CC(MIN.)

POWERDOWN PROTECTIONON INPUTS

AND OUTPUTS

SYMMETRICAL OUTPUT IMPEDANCE:

|I_OH| = I_OL= 8 mA (MIN)

BALANCEDPROPAGATIONDELAYS:

t_PLHt_PHL

SOT23-8L

ORDER CODES

PACKAGE

TUBE

T & R

SOT23-8L

74V2G00STR

wiring C²MOS technology.

The internal circuit is composed of 3 stages

including buffer output, which provide high noise

immunity and stable output.

OPERATING VOLTAGERANGE:

V_CC(OPR)= 2V to 5.5V

IMPROVED LATCH-UP IMMUNITY

DESCRIPTION

Power down protection is provided on all inputs

and outputs and 0 to 7V can be accepted on

inputs with no regard to the supply voltage. This

device can be used to interface 5V to 3V.

The 74V2G00 is an advanced high-speed CMOS

DUAL 2-INPUT NAND GATE fabricated with

sub-micron silicon gate and double-layer metal

PIN CONNECTION AND IEC LOGIC SYMBOLS

1/6

June 2000

12 3 4 5 6

中文翻译

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