Datasheet > 74AUP2G02DC

74AUP2G02DC

更新时间： 2023-09-03 20:29:10

品牌	Logo	应用领域
安世 - NEXPERIA		/
页数	文件大小	规格书
17页	264K
描述
Low-power dual 2-input NOR gateProduction

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数据手册

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74AUP2G02DC 数据手册

Nexperia

74AUP2G02

Low-power dual 2-input NOR gate

Symbol Parameter Conditions

C_L= 5 pF, 10 pF, 15 pF and 30 pF

T_amb= 25 °C

-40 °C to +85 °C -40 °C to +125 °C Unit

Min Typ[1] Max

Min

Max

Min

Max

C_PD

power

f_i= 1 MHz;

[3]

dissipation V_I= GND to V_CC

capacitance

V_CC= 0.8 V

2.6

2.7

2.8

2.9

3.3

3.8

V_CC= 1.1 V to 1.3 V

V_CC= 1.4 V to 1.6 V

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 3.0 V to 3.6 V

[1] All typical values are measured at nominal V_CC

[2] t_pdis the same as t_PLHand t_PHL

[3] C_PDis used to determine the dynamic power dissipation (P_Din μW).

P_D= C_PD× V_CC²× f_i× N + Σ(C_L× V_CC²× f_o) where:

f_i= input frequency in MHz;

f_o= output frequency in MHz;

C_L= output load capacitance in pF;

V_CC= supply voltage in V;

N = number of inputs switching;

Σ(C_L× V_CC²× f_o) = sum of the outputs.

11.1. Waveform and test circuit

nA, nB input

GND

PHL

PLH

nY output

mna213

Measurement points are given in Table 9.

Logic levels: V_OLand V_OHare typical output voltage levels that occur with the output load.

Fig. 6. The data input (nA, nB) to output (nY) propagation delays

Table 9. Measurement points

Supply voltage

V_CC

Output

V_M

Input

V_M

V_I

t_r= t_f

0.8 V to 3.6 V

0.5 × V_CC

V_CC

≤ 3.0 ns

74AUP2G02

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 9 — 27 July 2021

8 / 17

1...5 6 789 10 11...17

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