Datasheet > 74AUP2G02DC

74AUP2G02DC

更新时间： 2023-09-03 20:29:10

品牌	Logo	应用领域
安世 - NEXPERIA		/
页数	文件大小	规格书
17页	264K
描述
Low-power dual 2-input NOR gateProduction

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74AUP2G02DC 数据手册

Nexperia

74AUP2G02

Low-power dual 2-input NOR gate

EXT

5 kΩ

DUT

001aac521

Test data is given in Table 10.

Definitions for test circuit:

R_L= Load resistance.

C_L= Load capacitance including jig and probe capacitance.

R_T= Termination resistance should be equal to the output impedance Z_oof the pulse generator.

V_EXT= External voltage for measuring switching times.

Fig. 7. Test circuit for measuring switching times

Table 10. Test data

Supply voltage Load

V_EXT

V_CC

C_L

R_L[1]

t_PLH, t_PHL

open

t_PZH, t_PHZ

t_PZL, t_PLZ

0.8 V to 3.6 V

5 pF, 10 pF, 15 pF and 30 pF

5 kΩ or 1 MΩ

GND

2 × V_CC

[1] R_L= 5 kΩ when measuring enable and disable times.

R_L= 1 MΩ when measuring propagation delays, set-up and hold times and pulse width.

74AUP2G02

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 9 — 27 July 2021

9 / 17

1...6 7 8910 11 12...17

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