Datasheet > 74AUP2G02GD,125

74AUP2G02GD,125

更新时间： 2024-11-17 14:47:03

品牌	Logo	应用领域
恩智浦 - NXP		/
页数	文件大小	规格书
17页	83K
描述
74AUP2G02 - Low-power dual 2-input NOR gate SON 8-Pin

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74AUP2G02GD,125 技术参数

Source Url Status Check Date：	2013-06-14 00:00:00	是否Rohs认证：	符合
生命周期：	Transferred	零件包装代码：	SON
包装说明：	3 X 2 MM, 0.50 MM HEIGHT, PLASTIC, SOT996-2, SON-8	针数：	8
Reach Compliance Code：	compliant	风险等级：	5.75
Base Number Matches：	1

74AUP2G02GD,125 数据手册

74AUP2G02

Low-power dual 2-input NOR gate

Rev. 03 — 11 December 2008

Product data sheet

1. General description

The 74AUP2G02 provides a dual 2-input NOR function.

Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall

times across the entire V_CCrange from 0.8 V to 3.6 V.

This device ensures a very low static and dynamic power consumption across the entire

V_CCrange from 0.8 V to 3.6 V.

This device is fully speciﬁed for partial power-down applications using I_OFF. The I_OFF

circuitry disables the output, preventing a damaging backﬂow current through the device

when it is powered down.

2. Features

I Wide supply voltage range from 0.8 V to 3.6 V

I High noise immunity

I Complies with JEDEC standards:

N JESD8-12 (0.8 V to 1.3 V)

N JESD8-11 (0.9 V to 1.65 V)

N JESD8-7 (1.2 V to 1.95 V)

N JESD8-5 (1.8 V to 2.7 V)

N JESD8-B (2.7 V to 3.6 V)

I ESD protection:

N HBM JESD22-A114E Class 3A exceeds 5000 V

N MM JESD22-A115-A exceeds 200 V

N CDM JESD22-C101C exceeds 1000 V

I Low static power consumption; I_CC= 0.9 µA (maximum)

I Latch-up performance exceeds 100 mA per JESD78 Class II

I Inputs accept voltages up to 3.6 V

I Low noise overshoot and undershoot < 10 % of V_CC

I I_OFFcircuitry provides partial Power-down mode operation

I Multiple package options

I Speciﬁed from −40 °C to +85 °C and −40 °C to +125 °C

12 3 4 5 6 7...17

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