Datasheet > 74AUP2G04GM

74AUP2G04GM

更新时间： 2024-09-27 11:11:59

品牌	Logo	应用领域
安世 - NEXPERIA		/
页数	文件大小	规格书
18页	259K
描述
Low-power dual inverterProduction

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74AUP2G04GM 数据手册

74AUP2G04

Low-power dual inverter

Rev. 8 — 31 January 2022

Product data sheet

1. General description

The 74AUP2G04 is a dual inverter. Schmitt-trigger action at all inputs makes the circuit tolerant

of slower input rise and fall times. This device ensures very low static and dynamic power

consumption across the entire V_CCrange from 0.8 V to 3.6 V. This device is fully specified for

partial power down applications using I_OFF. The I_OFFcircuitry disables the output, preventing the

potentially damaging backflow current through the device when it is powered down.

2. Features and benefits

•

Wide supply voltage range from 0.8 V to 3.6 V

•

High noise immunity

Complies with JEDEC standards:

•

JESD8-12 (0.8 V to 1.3 V)

JESD8-11 (0.9 V to 1.65 V)

JESD8-7 (1.2 V to 1.95 V)

JESD8-5 (1.8 V to 2.7 V)

JESD8-B (2.7 V to 3.6 V)

•

ESD protection:

•

HBM JESD22-A114F Class 3A exceeds 5000 V

MM JESD22-A115-A exceeds 200 V

CDM JESD22-C101E exceeds 1000 V

•

Low static power consumption; I_CC= 0.9 μA (maximum)

Latch-up performance exceeds 100 mA per JESD 78 Class II

Inputs accept voltages up to 3.6 V

Low noise overshoot and undershoot < 10 % of V_CC

I_OFFcircuitry provides partial power-down mode operation

Multiple package options

Specified from -40 °C to +85 °C and -40 °C to +125 °C

12 3 4 5 6 7...18

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