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74AUP2G0604GM,125 PDF预览

74AUP2G0604GM,125

更新时间: 2024-11-18 20:53:23
品牌 Logo 应用领域
恩智浦 - NXP 光电二极管逻辑集成电路
页数 文件大小 规格书
20页 226K
描述
Inverter, AUP/ULP/V Series, 2-Func, 1-Input, CMOS, PDSO6

74AUP2G0604GM,125 技术参数

生命周期:Active包装说明:VSON,
Reach Compliance Code:unknown风险等级:5.66
系列:AUP/ULP/VJESD-30 代码:R-PDSO-N6
长度:1.45 mm逻辑集成电路类型:INVERTER
功能数量:2输入次数:1
端子数量:6最高工作温度:125 °C
最低工作温度:-40 °C输出特性:OPEN-DRAIN
封装主体材料:PLASTIC/EPOXY封装代码:VSON
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, VERY THIN PROFILE
传播延迟(tpd):21.3 ns座面最大高度:0.5 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):0.8 V
标称供电电压 (Vsup):1.1 V表面贴装:YES
技术:CMOS温度等级:AUTOMOTIVE
端子形式:NO LEAD端子节距:0.5 mm
端子位置:DUAL宽度:1 mm
Base Number Matches:1

74AUP2G0604GM,125 数据手册

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74AUP2G0604  
Low-power inverting buffer with open-drain and inverter  
Rev. 1 — 23 November 2012  
Product data sheet  
1. General description  
The 74AUP2G0604 is a single inverting buffer with open-drain output and a single  
inverter. It features two input pins (nA), an output pin (2Y) and an open-drain output pin  
(1Y).  
Schmitt trigger action at all inputs makes the circuit tolerant of slower input rise and fall  
times across the entire VCC range from 0.8 V to 3.6 V.  
This device ensures a very low static and dynamic power consumption across the entire  
VCC range from 0.8 V to 3.6 V.  
This device is fully specified for partial power-down applications using IOFF. The IOFF  
circuitry disables the output, preventing the damaging backflow current through the device  
when it is powered down.  
2. Features and benefits  
Wide supply voltage range from 0.8 V to 3.6 V  
High noise immunity  
Complies with JEDEC standards:  
JESD8-12 (0.8 V to 1.3 V)  
JESD8-11 (0.9 V to 1.65 V)  
JESD8-7 (1.2 V to 1.95 V)  
JESD8-5 (1.8 V to 2.7 V)  
JESD8-B (2.7 V to 3.6 V)  
ESD protection:  
HBM JESD22-A114F Class 3A exceeds 5000 V  
MM JESD22-A115-A exceeds 200 V  
CDM JESD22-C101E exceeds 1000 V  
Low static power consumption; ICC = 0.9 A (maximum)  
Latch-up performance exceeds 100 mA per JESD 78 Class II  
Inputs accept voltages up to 3.6 V  
Low noise overshoot and undershoot < 10 % of VCC  
IOFF circuitry provides partial power-down mode operation  
Multiple package options  
Specified from 40 C to +85 C and 40 C to +125 C  

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