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SI4922DY PDF预览

SI4922DY

更新时间: 2024-09-15 22:33:55
品牌 Logo 应用领域
威世 - VISHAY /
页数 文件大小 规格书
3页 197K
描述
SPICE Device Model Si4922DY

SI4922DY 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:,Reach Compliance Code:compliant
ECCN代码:EAR99风险等级:5.84
最大漏极电流 (Abs) (ID):6.7 AFET 技术:METAL-OXIDE SEMICONDUCTOR
JESD-609代码:e0工作模式:ENHANCEMENT MODE
最高工作温度:150 °C极性/信道类型:N-CHANNEL
最大功率耗散 (Abs):1.1 W子类别:FET General Purpose Powers
表面贴装:YES端子面层:Tin/Lead (Sn/Pb)
Base Number Matches:1

SI4922DY 数据手册

 浏览型号SI4922DY的Datasheet PDF文件第2页浏览型号SI4922DY的Datasheet PDF文件第3页 
SPICE Device Model Si4922DY  
Vishay Siliconix  
N-Channel 30-V (D-S) MOSFET  
CHARACTERISTICS  
N-Channel Vertical DMOS  
Macro Model (Subcircuit Model)  
Level 3 MOS  
Apply for both Linear and Switching Application  
Accurate over the 55 to 125°C Temperature Range  
Model the Gate Charge, Transient, and Diode Reverse Recovery  
Characteristics  
DESCRIPTION  
The attached spice model describes the typical electrical  
characteristics of the n-channel vertical DMOS. The subcircuit  
model is extracted and optimized over the 55 to 125°C  
temperature ranges under the pulsed 0-to-5V gate drive. The  
saturated output impedance is best fit at the gate bias near the  
threshold voltage.  
A novel gate-to-drain feedback capacitance network is used to model  
the gate charge characteristics while avoiding convergence difficulties  
of the switched Cgd model. All model parameter values are optimized  
to provide a best fit to the measured electrical data and are not  
intended as an exact physical interpretation of the device.  
SUBCIRCUIT MODEL SCHEMATIC  
This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate  
data sheet of the same number for guaranteed specification limits.  
Document Number: 71563  
16-Apr-01  
www.vishay.com  
1

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