MOSFET - Power, N-Channel
PowerTrench[ Power Clip
25 V Asymmetric Dual
NTTFD1D8N02P1E
Features
• Small Footprint (3.3mm x 3.3mm) for Compact Design
www.onsemi.com
• Low R
to Minimize Conduction Losses
DS(on)
• Low Q and Capacitance to Minimize Driver Losses
G
• These Devices are Pb−Free and are RoHS Compliant
FET
V
R
MAX
I MAX
D
(BR)DSS
DS(ON)
Typical Applications
• DC−DC Converters
• System Voltage Rails
4.2 mW @ 10 V
5.3 mW @ 4.5 V
1.4 mW @ 10 V
1.8 mW @ 4.5 V
Q1
25 V
61 A
Q2
25 V
126 A
MAXIMUM RATINGS (T = 25°C unless otherwise noted)
J
Parameter
Drain−to−Source Voltage
Gate−to−Source Voltage
Symbol
Q1
Q2
Unit
V
V
DSS
25
25
ELECTRICAL CONNECTION
V
GS
+16
−12
+16
−12
V
Continuous Drain
Current R
I
61
44
25
126
91
A
T
T
= 25°C
= 85°C
D
C
q
JC
Steady
(Note 3)
C
State
Power Dissipation
P
36
W
A
D
D
D
T
A
= 25°C
R
(Note 3)
q
JC
Continuous Drain
Current R
I
D
15
11
30
21
T
A
= 25°C
= 85°C
MARKING
DIAGRAM
q
JA
T
A
Steady
State
(Notes 1, 3)
Power Dissipation
P
I
1.6
2.0
W
A
T
A
= 25°C
R
(Notes 1, 3)
q
JA
Continuous Drain
Current R
11
8
21
15
T
A
= 25°C
= 85°C
D
q
JA
T
A
Steady
State
(Notes 2, 3)
Power Dissipation
P
0.8
0.9
W
T
A
= 25°C
R
(Notes 2, 3)
q
JA
2EMN = Specific Device Code
A
Y
WW
ZZ
= Assembly Location
= Year
= Work Week
= Assembly Lot Code
Pulsed Drain Current
T
= 25°C, t = 10 ms
I
DM
483
861
A
A
p
Single Pulse Drain−to−Source Avalanche
E
AS
37.3 150.
1
mJ
Energy
Q1: I = 15.8 A , L = 0.3 mH (Note 4)
L
pk
Q2: I = 31.63 A , L = 0.3 mH (Note 4)
L
pk
Operating Junction and Storage Temperature T , T
−55 to + 150
°C
°C
J
stg
ORDERING INFORMATION
Lead Temperature for Soldering
T
L
260
Purposes (1/8″ from case for 10 s)
†
Device
Package
Shipping
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
NTTFD1D8N02P1E
PQFN8
(Pb−Free)
3000 / Tape &
Reel
2
1. Surface−mounted on FR4 board using a 1 in pad size, 2 oz. Cu pad.
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
2. Surface−mounted on FR4 board using minimum pad size, 2 oz. Cu pad.
3. The entire application environment impacts the thermal resistance values shown,
they are not constants and are only valid for the particular conditions noted.
Actual continuous current will be limited by thermal & electro−mechanical
application board design. R
is determined by the user’s board design.
q
JC
4. Q1 100% UIS tested at L = 0.1 mH, IAS = 24.2 A.
Q2 100% UIS tested at L = 0.1 mH, IAS = 48.1 A.
5. This device does not have ESD protection diode.
© Semiconductor Components Industries, LLC, 2019
1
Publication Order Number:
February, 2020 − Rev. 1
NTTFD1D8N02P1E/D