NTTFS1D2N02P1E
MOSFET - Power, Single
N-Channel, Power33
25 V, 1.0 mW, 180 A
Features
• Small Footprint for Compact Design
www.onsemi.com
• Low R
to Minimize Conduction Losses
DS(on)
• Low Q and Capacitance to Minimize Driver Losses
G
V
R
MAX
I MAX
D
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
(BR)DSS
DS(ON)
Compliant
1.0 mW @ 10 V
1.2 mW @ 4.5 V
25 V
180 A
Typical Applications
• DC−DC Converters
• Power Load Switch
NMOS
• Notebook Battery Management
D (5−8)
MAXIMUM RATINGS (T = 25°C unless otherwise noted)
J
Parameter
Drain−to−Source Voltage
Symbol
Value
25
Unit
V
V
DSS
G (4)
Gate−to−Source Voltage
V
GS
+16/−12
180
V
Continuous Drain
T
T
T
= 25°C
= 85°C
= 25°C
I
D
A
C
C
C
S (1, 2, 3)
Current R
(Note 3)
q
JC
130
Steady
State
Power Dissipation
(Note 3)
P
52
W
A
D
D
D
MARKING
DIAGRAM
R
q
JC
Pin 1
Continuous Drain
Current R
T = 25°C
A
I
D
41
29
1
q
JA
T = 85°C
A
Steady
State
(Notes 1, 3)
2EJN
AYWWZZ
PQFN8
(Power33)
CASE 483AW
Power Dissipation
T = 25°C
A
P
2.7
W
A
R
(Notes 1, 3)
q
JA
Continuous Drain
Current R
T = 25°C
A
I
D
23
16
q
JA
2EJN
A
Y
WW
ZZ
= Specific Device Code
= Assembly Location
= Year
= Work Week
= Assembly Lot Code
T = 85°C
A
Steady
State
(Notes 2, 3)
Power Dissipation
T = 25°C
A
P
0.82
W
R
(Notes 2, 3)
q
JA
Pulsed Drain Current
T = 25°C, t = 10 ms
A
I
DM
195
202
A
p
Single Pulse Drain−to−Source Avalanche
E
AS
mJ
Energy (I = 63.7 A) (Note 4)
L(pk)
ORDERING INFORMATION
See detailed ordering and shipping information on page 5 of
this data sheet.
Operating Junction and Storage Temperature
Range
T , T
−55 to
°C
°C
J
stg
+150
Lead Temperature Soldering Reflow for Solder-
ing Purposes (1/8″ from case for 10 s)
T
L
260
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
2
1. Surface−mounted on FR4 board using a 1 in pad size, 2 oz Cu pad.
2. Surface−mounted on FR4 board using minimum pad size, 2 oz Cu pad.
3. The entire application environment impacts the thermal resistance values
shown. They are not constants and are only valid for the particular conditions
noted. Actual continuous current will be limited by thermal & electro−
mechanical application board design. R
is determined by the user’s board
q
CA
design.
4. 100% UIS tested at L = 0.1 mH, I = 40 A.
AV
© Semiconductor Components Industries, LLC, 2019
1
Publication Order Number:
September, 2019 − Rev. 1
NTTFS1D2N02P1E/D