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NDP6020 PDF预览

NDP6020

更新时间: 2024-09-19 22:29:07
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 晶体晶体管场效应晶体管
页数 文件大小 规格书
12页 377K
描述
N-Channel Logic Level Enhancement Mode Field Effect Transistor

NDP6020 数据手册

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November 1996  
NDP6020 / NDB6020  
N-Channel Logic Level Enhancement Mode Field Effect Transistor  
General Description  
Features  
These logic level N-Channel enhancement mode power  
field effect transistors are produced using National's  
proprietary, high cell density, DMOS technology. This  
very high density process has been especially tailored  
to minimize on-state resistance, provide superior  
switching performance, and withstand high energy  
pulses in the avalanche and commutation modes.  
These devices are particularly suited for low voltage  
applications such as automotive, DC/DC converters,  
PWM motor controls, and other battery powered  
circuits where fast switching, low in-line power loss,  
and resistance to transients are needed.  
35 A, 20 V. RDS(ON) = 0.023 W @ VGS= 4.5 V  
RDS(ON) = 0.028 W @ VGS= 2.7 V.  
Critical DC electrical parameters specified at elevated  
temperature.  
Rugged internal source-drain diode can eliminate the need  
for an external Zener diode transient suppressor.  
175°C maximum junction temperature rating.  
High density cell design for extremely low RDS(ON)  
.
TO-220 and TO-263 (D2PAK) package for both through  
hole and surface mount applications.  
_______________________________________________________________________________  
D
G
S
Absolute Maximum Ratings TC = 25°C unless otherwise noted  
Symbol  
Parameter  
NDP6020  
NDB6020  
Units  
V
VDSS  
Drain-Source Voltage  
20  
20  
VDGR  
V
Drain-Gate Voltage (RGS < 1 MW)  
Gate-Source Voltage - Continuous  
Drain Current - Continuous  
- Pulsed  
VGSS  
ID  
±8  
35  
V
A
100  
PD  
Total Power Dissipation @ TC = 25°C  
Derate above 25°C  
60  
W
W/°C  
°C  
0.4  
TJ,TSTG  
Operating and Storage Temperature Range  
-65 to 175  
© 1997 Fairchild Semiconductor Corporation  
NDP6020 Rev.C  

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