Datasheet > MPC949FAR2

MPC949FAR2

更新时间： 2024-11-11 19:48:43

品牌	Logo	应用领域
艾迪悌 - IDT		PC 驱动逻辑集成电路
页数	文件大小	规格书
4页	272K
描述
Low Skew Clock Driver, 949 Series, 15 True Output(s), 0 Inverted Output(s), CMOS, PQFP52, 10 X 10 MM, 0.65 MM PITCH, PLASTIC, LQFP-52

阅读下载

中文翻译

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

MPC949FAR2 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	LQFP,	针数：	52
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
风险等级：	5.26	系列：	949
输入调节：	DIFFERENTIAL MUX	JESD-30 代码：	S-PQFP-G52
JESD-609代码：	e0	长度：	10 mm
逻辑集成电路类型：	LOW SKEW CLOCK DRIVER	功能数量：	1
反相输出次数：		端子数量：	52
实输出次数：	15	最高工作温度：	70 °C
最低工作温度：		输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	LQFP
封装形状：	SQUARE	封装形式：	FLATPACK, LOW PROFILE
峰值回流温度（摄氏度）：	240	传播延迟（tpd）：	10.5 ns
认证状态：	Not Qualified	Same Edge Skew-Max（tskwd）：	0.35 ns
座面最大高度：	1.7 mm	最大供电电压 (Vsup)：	3.465 V
最小供电电压 (Vsup)：	3.135 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	TIN LEAD
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	20
宽度：	10 mm	最小 fmax：	160 MHz
Base Number Matches：	1

MPC949FAR2 数据手册

Freescale Semiconductor, Inc.

SEMICONDUCTOR TECHNICAL DATA

ꢀꢁ ꢂ ꢁꢃ ꢁ ꢄꢅ

Order this document

by MPC949/D

ꢄ

ꢓ

ꢆ

ꢀ

ꢇ

ꢁ

ꢈ

ꢔ

ꢆ

ꢓ

ꢉ

ꢊ

ꢋ

ꢌ

ꢍ

ꢎ ꢏꢎ ꢐ ꢑꢒ ꢓꢄ ꢊ ꢆ

ꢗꢘ ꢙꢚ ꢍ ꢘ

ꢀꢑ ꢓꢛ ꢜꢛ

See Upgrade Product – MPC9449

ꢉ

ꢆ

ꢕ

ꢖ

The MPC949 is a low voltage CMOS, 15 output clock buffer. The 15

outputs can be configured into a standard fanout buffer or into 1X and

1/2X combinations. The device features a low voltage PECL input, in

addition to its LVCMOS/LVTTL inputs, to allow it to be incorporated into

larger clock trees which utilize low skew PECL devices (see the

MC100EP111 data sheet) in the lower branches of the tree. The fifteen

outputs were designed and optimized to drive 50Ω series or parallel ter-

minated transmission lines. With output to output skews of 350ps the

MPC949 is an ideal clock distribution chip for synchronous systems

which need a tight level of skew from a large number of outputs. For a

similar product with a smaller fanout and package consult the MPC946

data sheet.

LOW VOLTAGE

1:15 PECL TO

LVCMOS CLOCK DRIVER

• Low Voltage PECL Clock Input

• 2 Selectable LVCMOS/LVTTL Clock Inputs

• 350ps Maximum Output to Output Skew

• Drives up to 30 Independent Clock Lines

• Maximum Output Frequency of 160MHz

• High Impedance Output Enable

• 52–Lead LQFP Packaging

FA SUFFIX

52–LEAD LQFP PACKAGE

CASE 848D

• 3.3V V_CCSupply

With an output impedance of approximately 7Ω, in both the HIGH and

the LOW logic states, the output buffers of the MPC949 are ideal for driv-

ing series terminated transmission lines. More specifically each of the 15

MPC949 outputs can drive two series terminated transmission lines. With

this capability, the MPC949 has an effective fanout of 1:30 in applications

using point–to–point distribution schemes.

The MPC949 has the capability of generating 1X and 1/2X signals from a 1X source. The design is fully static, the signals are

generated and retimed inside the chip to ensure minimal skew between the 1X and 1/2X signals. The device features selectability

to allow the user to select the ratio of 1X outputs to 1/2X outputs.

Two independent LVCMOS/LVTTL compatible clock inputs are available. Designers can take advantage of this feature to

provide redundant clock sources or the addition of a test clock into the system design. With the TCLK_Sel input pulled HIGH the

TCLK1 input is selected. The PCLK_Sel input will select the PECL input clock when driven HIGH.

All of the control inputs are LVCMOS/LVTTL compatible. The Dsel pins choose between 1X and 1/2X outputs. A LOW on the

Dsel pins will select the 1X output. The MR/OE input will reset the internal flip flops and tristate the outputs when it is forced HIGH.

The MPC949 is fully 3.3V compatible. The 52 lead LQFP package was chosen to optimize performance, board space and cost

of the device. The 52–lead LQFP has a 10x10mm body size with a 0.65mm pin spacing.

Rev 3

MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA

619

For More Information On This Product,

Go to: www.freescale.com

12 3 4

中文翻译

下载PDF

与MPC949FAR2相关器件

型号	品牌	获取价格	描述	数据表
MPC950	MOTOROLA	获取价格	LOW VOLTAGE PLL CLOCK DRIVER
MPC950FA	NXP	获取价格	IC,CPU SYSTEM CLOCK GENERATOR,CMOS,QFP,32PIN,PLASTIC
MPC950FA	IDT	获取价格	Processor Specific Clock Generator, 180MHz, CMOS, PQFP32, 7 X 7 MM, LQFP-32
MPC951	MOTOROLA	获取价格	LOW VOLTAGE PLL CLOCK DRIVER
MPC951FA	MOTOROLA	获取价格	LVCMOS/LVTTL SERIES, PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP3
MPC951FAR2	IDT	获取价格	PLL Based Clock Driver, 951 Series, 9 True Output(s), 0 Inverted Output(s), CMOS, PQFP32,
MPC952	MOTOROLA	获取价格	LOW VOLTAGE PLL CLOCK DRIVER
MPC952FA	NXP	获取价格	952 SERIES, PLL BASED CLOCK DRIVER, 11 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, PLAST
MPC952FA	IDT	获取价格	PLL Based Clock Driver, 952 Series, 11 True Output(s), 0 Inverted Output(s), CMOS, PQFP32,
MPC952FA	MOTOROLA	获取价格	LVCMOS/LVTTL SERIES, PLL BASED CLOCK DRIVER, 11 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP

与MPC949FAR2相关文章

国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

23
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

7
AMD宣布全球裁员约1000人，调整战略聚焦增长
2024-11-14

8
英伟达新AI芯片Rubin或提前半年亮相
2024-11-05

31

产品中心

服务支持

精选活动

关于我们

帮助中心

MPC949FAR2

MPC949FAR2 技术参数

MPC949FAR2 数据手册

与MPC949FAR2相关器件

与MPC949FAR2相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

MPC949FAR2

MPC949FAR2 技术参数

MPC949FAR2 数据手册

与MPC949FAR2相关器件

与MPC949FAR2相关文章

您还可以找

您在本页遇到什么问题？