Datasheet > MPC958FA

MPC958FA

更新时间： 2024-09-23 19:51:03

品牌	Logo	应用领域
恩智浦 - NXP		驱动输出元件
页数	文件大小	规格书
8页	251K
描述
958 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X 7 MM, PLASTIC, LQFP-32

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MPC958FA 技术参数

是否Rohs认证：	不符合	生命周期：	Transferred
零件包装代码：	QFP	包装说明：	7 X 7 MM, PLASTIC, LQFP-32
针数：	32	Reach Compliance Code：	not_compliant
HTS代码：	8542.39.00.01	风险等级：	5.47
系列：	958	输入调节：	DIFFERENTIAL
JESD-30 代码：	S-PQFP-G32	JESD-609代码：	e0
长度：	7 mm	逻辑集成电路类型：	PLL BASED CLOCK DRIVER
湿度敏感等级：	2	功能数量：	1
反相输出次数：		端子数量：	32
实输出次数：	10	最高工作温度：	70 °C
最低工作温度：		输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	LQFP
封装形状：	SQUARE	封装形式：	FLATPACK, LOW PROFILE
传播延迟（tpd）：	7 ns	认证状态：	Not Qualified
Same Edge Skew-Max（tskwd）：	0.2 ns	座面最大高度：	1.6 mm
最大供电电压 (Vsup)：	3.465 V	最小供电电压 (Vsup)：	3.135 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING	端子节距：	0.8 mm
端子位置：	QUAD	宽度：	7 mm
最小 fmax：	100 MHz	Base Number Matches：	1

MPC958FA 数据手册

Freescale Semiconductor, Inc.

SEMICONDUCTOR TECHNICAL DATA

Order this document

by MPC958/D

The MPC958 is a 3.3V compatible, PLL based clock driver device

targeted for high performance clock tree designs. With output frequencies

of up to 200MHz and output skews of 200ps the MPC958 is ideal for the

most demanding clock tree designs. The devices employ a fully

differential PLL design to minimize cycle–to–cycle and phase jitter.

LOW VOLTAGE

PLL CLOCK DRIVER

• Fully Integrated PLL

• Output Frequency up to 200MHz

• Outputs Disable in High Impedance

• LQFP Packaging

• 100ps Cycle–to–Cycle Jitter

The MPC958 has a differential LVPECL reference input along with an

external feedback input. These features make the MPC958 ideal for use

as a zero delay, low skew fanout buffer. The device performance has

been tuned and optimized for zero delay performance. The MR/OE input

pin will tristate the output buffers when driven “high”.

FA SUFFIX

32–LEAD LQFP PACKAGE

CASE 873A–02

The MPC958 is fully 3.3V compatible and requires no external loop

filter components. All control inputs accept LVCMOS or LVTTL

compatible levels while the outputs provide LVCMOS levels with the

ability to drive terminated 50Ω transmission lines. For series terminated

50Ω lines, each of the MPC958 outputs can drive two traces giving the

device an effective fanout of 1:22. The device is packaged in a 7x7mm

32–lead LQFP package to provide the optimum combination of board

density and performance.

QFB

Q0:8

(Int pull up)

PECL_CLK

(Int pull down)

Phase

Detector

VCO

200–400MHz

LPF

÷2

(Int pull up)

÷2

FB_CLK

(Int pull up)

(Int pull down)

(Int pull up)

VCO_SEL

BYPASS

MR/OE

PLL_EN

Figure 1. Logic Diagram

06/00

Motorola, Inc. 2000

For More Information On This Product,

Go to: www.freescale.c^Ro^Em^{V 1}

12 3 4 5 6 7 8

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与MPC958FA相关器件

型号	品牌	获取价格	描述	数据表
MPC958FAR2	MOTOROLA	获取价格	MPC900 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7
MPC958FAR2	NXP	获取价格	958 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X 7
MPC9600	MOTOROLA	获取价格	LOW VOLTAGE 2.5 V AND 3.3 V CMOS PLL CLOCK DRIVER
MPC9600AE	IDT	获取价格	Low Voltage, 2.5V and 3.3V LVCMOS PLL Clock Driver
MPC9600FA	FREESCALE	获取价格	LOW VOLTAGE 2.5V AND 3.3 V CMOS PLL CLOCK DRIVER
MPC9600FAR2	MOTOROLA	获取价格	PLL Based Clock Driver, 21 True Output(s), 0 Inverted Output(s), CMOS, PQFP48, PLASTIC, LQ
MPC9600FAR2	NXP	获取价格	9600 SERIES, PLL BASED CLOCK DRIVER, 21 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP48, PLAS
MPC9608	MOTOROLA	获取价格	1:10 LVCMOS Zero Delay Clock Buffer
MPC9608AC	MOTOROLA	获取价格	PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X 7 MM, LEAD FR
MPC9608AC	NXP	获取价格	9608 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X

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