MPC9608

更新时间： 2024-09-22 22:51:11

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		时钟
页数	文件大小	规格书
12页	425K
描述
1:10 LVCMOS Zero Delay Clock Buffer

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数据手册

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MPC9608 数据手册

Freescale Semiconductor, Inc.

MOTOROLA

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SEMICONDUCTOR TECHNICAL DATA

MPC9608

1:10 LVCMOS Zero Delay

Clock Buffer

The MPC9608 is a 3.3 V compatible, 1:10 PLL based zero-delay buffer. With a

very wide frequency range and low output skews the MPC9608 is targeted for

high performance and mid-range clock tree designs.

LOW VOLTAGE 3.3 V

LVCMOS 1:10 ZERO-DELAY

CLOCK BUFFER

Features

• 1:10 outputs LVCMOS zero-delay buffer

• Single 3.3 V supply

• Supports a clock I/O frequency range of 12.5 to 200 MHz

• Selectable divide-by-two for one output bank

• Synchronous output enable control (CLK_STOP)

• Output tristate control (output high impedance)

• PLL bypass mode for low frequency system test purpose

• Supports networking, telecommunications and computer applications

• Supports a variety of microprocessors and controllers

• Compatible to PowerQuicc I and II

FA SUFFIX

32-LEAD LQFP PACKAGE

CASE 873A

• Ambient Temperature Range -40°C to +85°C

• 32-lead Pb-free package available

AC SUFFIX

32 LEAD LQFP PACKAGE-Pb-free

CASE 873A

Functional Description

The MPC9608 uses an internal PLL and an external feedback path to lock its

low-skew clock output phase to the reference clock phase, providing virtually zero

propagation delay. This enables nested clock designs with near-zero insertion

delay. Designs using the MPC9608 as PLL fanout buffer will show significantly lower clock skew than clock distributions developed

from traditional fanout buffers. The device offers one reference clock input and two banks of 5 outputs for clock fanout. The input

frequency and phase is reproduced by the PLL and provided at the outputs. A selectable frequency divider sets the bank B outputs

to generate either an identical copy of the bank A clocks or one half of the bank A clock frequency. Both output banks remain syn-

chronized to the input reference for both bank B configurations.

Outputs are only disabled or enabled when the outputs are already in logic low state (CLK_STOP). For system test and diagnosis,

the MPC9608 outputs can also be set to high-impedance state by connecting OE to logic high level. Additionally, the device provides

a PLL bypass mode for low frequency test purpose. In PLL bypass mode, the minimum frequency and static phase offset specification

do not apply.

CLK_STOP and OE do not affect the PLL feedback output (QFB) and down stream clocks can be disabled without the internal PLL

losing lock.

The MPC9608 is fully 3.3 V compatible and requires no external components for the internal PLL. All inputs accept LVCMOS sig-

nals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 Ω transmission lines on the inci-

dent edge. For series terminated transmission lines, each of the MPC9608 outputs can drive one or two traces giving the devices an

effective fanout of 1:20. The device is packaged in a 7x7 mm²32-lead LQFP package.

REV 2

For More Information On This Product,

Go to: www.freescale.com

12 3 4 5 6 7...12

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与MPC9608相关器件

型号	品牌	获取价格	描述	数据表
MPC9608AC	MOTOROLA	获取价格	PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X 7 MM, LEAD FR
MPC9608AC	NXP	获取价格	9608 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X
MPC9608ACR2	IDT	获取价格	PLL Based Clock Driver, 9608 Series, 10 True Output(s), 0 Inverted Output(s), CMOS, PQFP32
MPC9608ACR2	NXP	获取价格	9608 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X
MPC9608FA	MOTOROLA	获取价格	PLL Based Clock Driver, 10 True Output(s), 0 Inverted Output(s), CMOS, PQFP32, 7 X 7 MM, L
MPC9608FA	NXP	获取价格	IC,1:10 OUTPUT,LV-CMOS,QFP,32PIN,PLASTIC
MPC9608FAR2	MOTOROLA	获取价格	PLL Based Clock Driver, 10 True Output(s), 0 Inverted Output(s), CMOS, PQFP32, 7 X 7 MM, L
MPC9608FAR2	IDT	获取价格	PLL Based Clock Driver, 9608 Series, 10 True Output(s), 0 Inverted Output(s), CMOS, PQFP32
MPC9608FAR2	NXP	获取价格	IC,1:10 OUTPUT,CMOS,QFP,32PIN,PLASTIC
MPC961C	MOTOROLA	获取价格	LOW VOLTAGE ZERO DELAY

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