Datasheet > MPC952

MPC952

更新时间： 2024-09-22 22:51:11

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		时钟驱动器
页数	文件大小	规格书
7页	110K
描述
LOW VOLTAGE PLL CLOCK DRIVER

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MPC952 数据手册

SEMICONDUCTOR TECHNICAL DATA

The MPC952 is a 3.3V compatible, PLL based clock driver device

targeted for high performance clock tree applications. The device

features a fully integrated PLL with no external components required.

With output frequencies of up to 180MHz and eleven low skew outputs

the MPC952 is well suited for high performance designs. The device

employs a fully differential PLL design to optimize jitter and noise

rejection performance. Jitter is an increasingly important parameter as

more microprocessors and ASiC’s are employing on chip PLL clock

distribution.

LOW VOLTAGE

PLL CLOCK DRIVER

• Fully Integrated PLL

• Output Frequency up to 180MHz

• High Impedance Disabled Outputs

• Compatible with PowerPC , Intel and High Performance RISC

Microprocessors

• Output Frequency Configurable

• TQFP Packaging

• ±100ps Cycle–to–Cycle Jitter

FA SUFFIX

TQFP PACKAGE

CASE 873A-02

The MPC952 features three banks of individually configurable outputs.

The banks contain 5 outputs, 4 outputs and 2 outputs. The internal divide

circuitry allows for output frequency ratios of 1:1, 2:1, 3:1 and 3:2:1. The

output frequency relationship is controlled by the fsel frequency control

pins. The fsel pins as well as the other inputs are LVCMOS/LVTTL

compatible inputs.

The MPC952 uses external feedback to the PLL. This features allows

for the use of the device as a “zero delay” buffer. Any of the eleven

outputs can be used as the feedback to the PLL. The VCO_Sel pin allows for the choice of two VCO ranges to optimize PLL

stability and jitter performance. The MR/OE pin allows the user to force the outputs into high impedance for board level test.

For system debug the PLL of the MPC952 can be bypassed. When forced to a logic HIGH, the PLLEN input will route the

signal on the RefClk input around the PLL directly to the internal dividers. Because the signal is routed through the dividers, it

may take several transitions of the RefClk to affect a transition on the outputs. This features allows a designer to single step the

design for debug purposes.

The outputs of the MPC952 are LVCMOS outputs. The outputs are optimally designed to drive terminated transmission lines.

For applications using series terminated transmission lines each MPC952 output can drive two lines. This capability provides an

effective fanout of 22, more than enough clocks for most clock tree designs. For more information on driving transmission lines

consult the applications section of this data sheet.

PowerPC is a trademark of International Business Machines Corporation. Pentium is a trademark of Intel Corporation.

2/98

REV 3

Motorola, Inc. 1998

12 3 4 5 6 7

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与MPC952相关器件

型号	品牌	获取价格	描述	数据表
MPC952FA	NXP	获取价格	952 SERIES, PLL BASED CLOCK DRIVER, 11 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, PLAST
MPC952FA	IDT	获取价格	PLL Based Clock Driver, 952 Series, 11 True Output(s), 0 Inverted Output(s), CMOS, PQFP32,
MPC952FA	MOTOROLA	获取价格	LVCMOS/LVTTL SERIES, PLL BASED CLOCK DRIVER, 11 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP
MPC952FAR2	IDT	获取价格	PLL Based Clock Driver, 952 Series, 11 True Output(s), 0 Inverted Output(s), CMOS, PQFP32,
MPC953	MOTOROLA	获取价格	LOW VOLTAGE PLL CLOCK DRIVER
MPC953FAR2	MOTOROLA	获取价格	PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X 7 MM, PLASTIC,
MPC954DT	MOTOROLA	获取价格	MPC900 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24, TS
MPC954DT	NXP	获取价格	IC,1:10 OUTPUT,BIPOLAR,TSSOP,24PIN,PLASTIC
MPC954DT	IDT	获取价格	PLL Based Clock Driver, 954 Series, 10 True Output(s), 0 Inverted Output(s), PDSO24, TSSOP
MPC954DTR2	MOTOROLA	获取价格	MPC900 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24, TS

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