Datasheet > MPC9600FAR2

MPC9600FAR2

更新时间： 2024-11-11 21:02:27

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		/
页数	文件大小	规格书
16页	185K
描述
PLL Based Clock Driver, 21 True Output(s), 0 Inverted Output(s), CMOS, PQFP48, PLASTIC, LQFP-48

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MPC9600FAR2 数据手册

Order Number: MPC9600/D

Rev. 2, 11/2001

SEMICONDUCTOR TECHNICAL DATA

The MPC9600 is a low voltage 2.5 V or 3.3 V compatible, 1:21 PLL

based clock driver and fanout buffer. With output frequencies up to 200

MHz and output skews of 150 ps, the device meets the needs of the most

demanding clock tree applications.

Features:

•

Multiplication of input frequency by 2, 3, 4 and 6

•

Distribution of output frequency to 21 outputs organized in three output

banks: QA0-QA6, QB0-QB6, QC0-QC6, each fully selectable

3.3 V OR 2.5 V

LOW VOLTAGE CMOS

PLL CLOCK DRIVER

•

Fully integrated PLL

Selectable output frequency range is 50 to 100 MHz and 100 to 200 MHz

Selectable input frequency range is 16.67 to 33 MHz and 25 to 50 MHz

LVCMOS outputs

Outputs disable to high impedance (except QFB)

LVCMOS or LVPECL reference clock options

48 lead QFP packaging

±50 ps cycle-to-cycle jitter

150 ps maximum output-to-output skew

200 ps maximum static phase offset window

FA SUFFIX

48–LEAD LQFP PACKAGE

CASE 932–03

The MPC9600 is a fully LVCMOS 2.5 V or 3.3 V compatible PLL clock

driver. The MPC9600 has the capability to generate clock signals of 50 to

200 MHz from clock sources of 16.67 to 50 MHz. The internal PLL is

optimized for this frequency range and does not require external loop filter

components. QFB provides an output for the external feedback path to

the feedback input FB_IN. The QFB divider ratio is configurable and

determines the PLL frequency multiplication factor when QFB is directly

connected to FB_IN. The MPC9600 is optimized for minimizing the

propagation delay between the clock input and FB_IN.

Three output banks of 7 outputs each bank can be individually configured to divide the VCO frequency by 2 or by 4. Combining

the feedback and output divider ratios, the MPC9600 is capable to multiply the input frequency by 2, 3, 4 and 6.

The reference clock is selectable either LVPECL or LVCMOS. The LVPECL reference clock feature allows the designer to use

LVPECL fanout buffers for the inner branches of the clock distribution tree. All control inputs accept LVCMOS compatible levels.

The outputs provide low impedance LVCMOS outputs capable of driving parallel terminated 50 Ω transmission to V =V /2.

TT CC

For series terminated lines the MPC9600 can drive two lines per output giving the device an effective total fanout of 1:42. With

guaranteed maximum output-to-output skew of 150 ps, the MPC9600 PLL clock driver meets the synchronization requirements

of the most demanding systems.

The V

analog power pin doubles as a PLL bypass select line for test purpose. When the V

is driven to GND the

CCA

reference clock will bypass the PLL.

The device is packaged in a 48-lead LQFP package to provide optimum combination of board density and performance.

Motorola, Inc. 2001

12 3 4 5 6 7...16

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与MPC9600FAR2相关器件

型号	品牌	获取价格	描述	数据表
MPC9608	MOTOROLA	获取价格	1:10 LVCMOS Zero Delay Clock Buffer
MPC9608AC	MOTOROLA	获取价格	PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X 7 MM, LEAD FR
MPC9608AC	NXP	获取价格	9608 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X
MPC9608ACR2	IDT	获取价格	PLL Based Clock Driver, 9608 Series, 10 True Output(s), 0 Inverted Output(s), CMOS, PQFP32
MPC9608ACR2	NXP	获取价格	9608 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X
MPC9608FA	MOTOROLA	获取价格	PLL Based Clock Driver, 10 True Output(s), 0 Inverted Output(s), CMOS, PQFP32, 7 X 7 MM, L
MPC9608FA	NXP	获取价格	IC,1:10 OUTPUT,LV-CMOS,QFP,32PIN,PLASTIC
MPC9608FAR2	MOTOROLA	获取价格	PLL Based Clock Driver, 10 True Output(s), 0 Inverted Output(s), CMOS, PQFP32, 7 X 7 MM, L
MPC9608FAR2	IDT	获取价格	PLL Based Clock Driver, 9608 Series, 10 True Output(s), 0 Inverted Output(s), CMOS, PQFP32
MPC9608FAR2	NXP	获取价格	IC,1:10 OUTPUT,CMOS,QFP,32PIN,PLASTIC

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