MPC962305D-1H

更新时间： 2024-09-22 22:06:35

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		时钟驱动器逻辑集成电路光电二极管
页数	文件大小	规格书
12页	447K
描述
Low-Cost 3.3 V Zero Delay Buffer

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MPC962305D-1H 数据手册

Freescale Semiconductor, Inc.

MOTOROLA

Order number: MPC962305

Rev 5, 08/2004

SEMICONDUCTOR TECHNICAL DATA

MPC962305

MPC962309

Low-Cost 3.3 V Zero Delay Buffer

The MPC962309 is a zero delay buffer designed to distribute high-speed

clocks. Available in a 16-pin SOIC or TSSOP package, the device accepts one

reference input and drives nine low-skew clocks. The MPC962305 is the 8-pin

version of the MPC962309 which drives five outputs with one reference input.

The -1H versions of these devices have higher drive than the -1 devices and

can operate up to 100/-133 MHz frequencies. These parts have on-chip PLLs

which lock to an input clock presented on the REF pin. The PLL feedback is

on-chip and is obtained from the CLOCKOUT pad.

D SUFFIX

8-LEAD SOIC PACKAGE

CASE 751-06

Features

•

1:5 LVCMOS zero-delay buffer (MPC962305)

1:9 LVCMOS zero-delay buffer (MPC962309)

Zero input-output propagation delay

Multiple low-skew outputs

DT SUFFIX

8-LEAD TSSOP PACKAGE

CASE 948J-01

250 ps max output-output skew

700 ps max device-device skew

Supports a clock I/O frequency range of 10 MHz to 133 MHz,

compatible with CPU and PCI bus frequencies

D SUFFIX

16-LEAD SOIC PACKAGE

CASE 751B-05

•

Low jitter, 200 ps max cycle-cycle, and compatible with Pentium^®based

systems

•

Test Mode to bypass PLL (MPC962309 only. See “Select Input Decoding”)

8-pin SOIC or 8-pin TSSOP package (MPC962305);16-pin SOIC or 16-pin

TSSOP package (MPC962309)

•

Single 3.3 V supply

Ambient temperature range: –40°C to +85°C

Compatible with the CY2305, CY23S05, CY2309, CY23S09

Spread spectrum compatible

DT SUFFIX

16-LEAD TSSOP PACKAGE

CASE 948F-01

Functional Description

The MPC962309 has two banks of four outputs each, which can be con-

trolled by the Select Inputs as shown in Table 3.Select Input Decoding for

MPC962309. Bank B can be tri-stated if all of the outputs are not required. Select inputs also allow the input clock to be directly applied

to the outputs for chip and system testing purposes.

The MPC962305 and MPC962309 PLLs enters a power down state when there are no rising edges on the REF input. During this

state, all of the outputs are in tristate, the PLL is turned off, and there is less than 25.0 µA of current draw for the device. The PLL

shuts down in one additional case as shown in Table 3.Select Input Decoding for MPC962309.

Multiple MPC962305 and MPC962309 devices can accept the same input clock and distribute it throughout the system. In this

situation, the difference between the output skews of two devices will be less than 700 ps.

All outputs have less than 200 ps of cycle-cycle jitter. The input-to-output propagation delay on both devices is guaranteed to be

less than 350 ps and the output-to-output skew is guaranteed to be less than 250 ps.

The MPC962305 and MPC962309 are available in two/three different configurations, as shown on the ordering information page.

The MPC962305-1/MPC962309-1 are the base parts. High drive versions of those devices, MPC962305-1H and MPC962309-1H,

are available to provide faster rise and fall times of the base device.

For More Information On This Product,

Go to: www.freescale.com

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与MPC962305D-1H相关器件

型号	品牌	获取价格	描述	数据表
MPC962305D-1HR2	MOTOROLA	获取价格	Low-Cost 3.3 V Zero Delay Buffer
MPC962305D-1HR2	IDT	获取价格	Low-Cost, 3.3V Zero Delay Buffer
MPC962305D-1HR2	NXP	获取价格	IC,1:5 OUTPUT,SOP,8PIN,PLASTIC
MPC962305D-1R2	MOTOROLA	获取价格	Low-Cost 3.3 V Zero Delay Buffer
MPC962305D-1R2	NXP	获取价格	962305 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8, 0.15
MPC962305D-1R2	IDT	获取价格	Low-Cost, 3.3V Zero Delay Buffer
MPC962305DT-1H	MOTOROLA	获取价格	Low-Cost 3.3 V Zero Delay Buffer
MPC962305DT-1H	IDT	获取价格	Low-Cost, 3.3V Zero Delay Buffer
MPC962305DT-1H	NXP	获取价格	IC,1:5 OUTPUT,TSSOP,8PIN,PLASTIC
MPC962305DT-1HR2	MOTOROLA	获取价格	Low-Cost 3.3 V Zero Delay Buffer

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