MPC9608AC

更新时间： 2024-11-11 13:11:47

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		时钟
页数	文件大小	规格书
12页	425K
描述
PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X 7 MM, LEAD FREE, LQFP-32

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MPC9608AC 技术参数

生命周期：	Transferred	零件包装代码：	QFP
包装说明：	LQFP, QFP32,.35SQ,32	针数：	32
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.26	Is Samacsys：	N
输入调节：	STANDARD	JESD-30 代码：	S-PQFP-G32
长度：	7 mm	逻辑集成电路类型：	PLL BASED CLOCK DRIVER
功能数量：	1	反相输出次数：
端子数量：	32	实输出次数：	10
最高工作温度：	85 °C	最低工作温度：	-40 °C
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	LQFP	封装形状：	SQUARE
封装形式：	FLATPACK, LOW PROFILE	认证状态：	Not Qualified
Same Edge Skew-Max（tskwd）：	0.1 ns	座面最大高度：	1.6 mm
最大供电电压 (Vsup)：	3.465 V	最小供电电压 (Vsup)：	3.135 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
温度等级：	INDUSTRIAL	端子形式：	GULL WING
端子节距：	0.8 mm	端子位置：	QUAD
宽度：	7 mm	最小 fmax：	100 MHz
Base Number Matches：	1

MPC9608AC 数据手册

Freescale Semiconductor, Inc.

MOTOROLA

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by MPC9608

SEMICONDUCTOR TECHNICAL DATA

MPC9608

1:10 LVCMOS Zero Delay

Clock Buffer

The MPC9608 is a 3.3 V compatible, 1:10 PLL based zero-delay buffer. With a

very wide frequency range and low output skews the MPC9608 is targeted for

high performance and mid-range clock tree designs.

LOW VOLTAGE 3.3 V

LVCMOS 1:10 ZERO-DELAY

CLOCK BUFFER

Features

• 1:10 outputs LVCMOS zero-delay buffer

• Single 3.3 V supply

• Supports a clock I/O frequency range of 12.5 to 200 MHz

• Selectable divide-by-two for one output bank

• Synchronous output enable control (CLK_STOP)

• Output tristate control (output high impedance)

• PLL bypass mode for low frequency system test purpose

• Supports networking, telecommunications and computer applications

• Supports a variety of microprocessors and controllers

• Compatible to PowerQuicc I and II

FA SUFFIX

32-LEAD LQFP PACKAGE

CASE 873A

• Ambient Temperature Range -40°C to +85°C

• 32-lead Pb-free package available

AC SUFFIX

32 LEAD LQFP PACKAGE-Pb-free

CASE 873A

Functional Description

The MPC9608 uses an internal PLL and an external feedback path to lock its

low-skew clock output phase to the reference clock phase, providing virtually zero

propagation delay. This enables nested clock designs with near-zero insertion

delay. Designs using the MPC9608 as PLL fanout buffer will show significantly lower clock skew than clock distributions developed

from traditional fanout buffers. The device offers one reference clock input and two banks of 5 outputs for clock fanout. The input

frequency and phase is reproduced by the PLL and provided at the outputs. A selectable frequency divider sets the bank B outputs

to generate either an identical copy of the bank A clocks or one half of the bank A clock frequency. Both output banks remain syn-

chronized to the input reference for both bank B configurations.

Outputs are only disabled or enabled when the outputs are already in logic low state (CLK_STOP). For system test and diagnosis,

the MPC9608 outputs can also be set to high-impedance state by connecting OE to logic high level. Additionally, the device provides

a PLL bypass mode for low frequency test purpose. In PLL bypass mode, the minimum frequency and static phase offset specification

do not apply.

CLK_STOP and OE do not affect the PLL feedback output (QFB) and down stream clocks can be disabled without the internal PLL

losing lock.

The MPC9608 is fully 3.3 V compatible and requires no external components for the internal PLL. All inputs accept LVCMOS sig-

nals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 Ω transmission lines on the inci-

dent edge. For series terminated transmission lines, each of the MPC9608 outputs can drive one or two traces giving the devices an

effective fanout of 1:20. The device is packaged in a 7x7 mm²32-lead LQFP package.

REV 2

For More Information On This Product,

Go to: www.freescale.com

12 3 4 5 6 7...12

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与MPC9608AC相关器件

型号	品牌	获取价格	描述	数据表
MPC9608ACR2	IDT	获取价格	PLL Based Clock Driver, 9608 Series, 10 True Output(s), 0 Inverted Output(s), CMOS, PQFP32
MPC9608ACR2	NXP	获取价格	9608 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X
MPC9608FA	MOTOROLA	获取价格	PLL Based Clock Driver, 10 True Output(s), 0 Inverted Output(s), CMOS, PQFP32, 7 X 7 MM, L
MPC9608FA	NXP	获取价格	IC,1:10 OUTPUT,LV-CMOS,QFP,32PIN,PLASTIC
MPC9608FAR2	MOTOROLA	获取价格	PLL Based Clock Driver, 10 True Output(s), 0 Inverted Output(s), CMOS, PQFP32, 7 X 7 MM, L
MPC9608FAR2	IDT	获取价格	PLL Based Clock Driver, 9608 Series, 10 True Output(s), 0 Inverted Output(s), CMOS, PQFP32
MPC9608FAR2	NXP	获取价格	IC,1:10 OUTPUT,CMOS,QFP,32PIN,PLASTIC
MPC961C	MOTOROLA	获取价格	LOW VOLTAGE ZERO DELAY
MPC961CAC	IDT	获取价格	TQFP-32, Tray
MPC961CAC	NXP	获取价格	961 SERIES, PLL BASED CLOCK DRIVER, 17 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, PLAST

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